Posted 21 days ago
Analogue RF IC Designer for EM Simulation Tasks
@ Braintrust
Canada
Overview
Braintrust is hiring a full-time analogue RF IC designer to write evaluation tasks in which a model designs a passive on-chip component to a spec, simulates it and iterates. The work covers laying out passives, running EM simulations, and writing Python checks that re-simulate submitted layouts. Work is remote, with the role open to candidates in Europe, Canada and the US, and the final rate depends on qualifications, expertise, experience and location.
Responsibilities:
- Write eval tasks for on-chip passive component design
- Write specs and reference designs for each task
- Build automatic checks that re-simulate submitted layouts
- Run a pilot of 5 tasks and iterate before scaling
Requirements summary:
- Hands-on RF IC design and passive layout experience
- EM simulation experience and reading S-parameters, inductance and Q
- Works with GDS layouts and S-parameter files
- Enough Python to script simulations and write checks
Tools & skills
Source and dates
Source type not verified · apify-linkedin
- Employer posting date
- 2026-10-23
- First seen by our source
- 2026-11-14
- Source record updated
- 2026-11-14
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Mid level |
| Department | Engineering |
| Hours per week | 40 (estimated) |
| Travel | air: none · ground: none |
| Work setting | Home |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Braintrust
| Field | Value |
|---|---|
| Open jobs on Jobsy | 9 |
- Write new eval tasks where a model designs one passive on-chip component to a spec (e.g., a spiral inductor with a target inductance, quality factor and area), then simulates it and iterates.
- For each task, write the spec, a reference design that meets it and an automatic check that re-simulates the submitted layout and compares the results with the spec.
- Start with a pilot of 5 tasks, then iterate with us before scaling.
- Hands-on RF IC design, including laying out passives (e.g., spiral inductors, transformers and baluns, transmission lines, coupled resonators, quadrature hybrids).
- Has run EM simulations on their own layouts and can read the results (e.g., S-parameters, inductance and quality factor).
- Works with GDS layouts and S-parameter files.
- Enough Python to script simulations and write the checks.
- Experience with IHP SG13G2 or another open PDK (our test chip is a 24 GHz radar receiver front end on SG13G2).
- The open-source tools we use: KLayout, Palace, openEMS, ngspice, scikit-rf. We can share our container (IIC-OSIC-TOOLS).
- Commercial EM solvers (e.g., Cadence EMX or Ansys HFSS).
- SPICE simulation of RF blocks (e.g., a low noise amplifier), which we'd like to cover later.
Final rate depends on qualifications, expertise, experience, and location
Journal
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