Firmware Engineer – SerDes PHY (all levels)

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > Software Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Replacement Position

Minimum Qualifications:

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience.
OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience.
OR
PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience.

• 3+ years of work experience with Programming Language such as C, C++, Java, Python, etc.

We’re building the world’s most advanced SerDes PHY for use in AI data centers and beyond. The Embedded Software / Firmware Team at Qualcomm develops critical embedded software that powers high-performance multi-standard Serializer/Deserializer (SerDes) PHY IP used in next-generation data center, AI/ML, automotive, and compute applications. Our SerDes IPs support standards such as PCIe, Ethernet, CXL, and are integrated into SoCs, ASICs, and chiplets built by leading semiconductor companies around the world.

The firmware team owns the full embedded software stack that controls the SerDes hardware, including low-level embedded firmware, customer-facing C SDKs, demo & automation scripts, and interactive tools. As a key enabler of silicon bring-up, validation, and production deployment, we work closely with hardware, systems, DV, validation, and application teams across the product lifecycle—from early development to high-volume manufacturing.

We are looking for an experienced Firmware Engineer to lead firmware architecture, development, integration, and bring-up for our SerDes PHY portfolio. The ideal candidate has driven firmware definition, architecture, and development starting from the RTL/digital design phase with EDA tool/simulator integration, all the way through to the post-silicon phase with device-level bring-up and debug. This is a highly collaborative role: you will work with hardware, systems, and software teams to drive requirements and successful chip bring-up; with firmware and embedded software engineers to drive code re-use across the organization; and with program managers to identify and meet deadlines. This individual will be instrumental in building next-generation SERDES PHY IP and semiconductors that meet Qualcomm’s high performance and quality standards.

What You Can Expect

Core responsibilities for the firmware team include:

Embedded firmware running on RISC-V-based controllers that manage Qualcomm’s advanced SerDes datapaths

Python and C SDKs provided to internal SoC teams and external customers for SerDes bring-up, calibration, tuning, and diagnostics

Python-based lab tools and GUIs for interactive debug, register access, and validation

Build, regression, and CI infrastructure to ensure code quality and full coverage.

You’ll play a key leadership role in delivering robust, production-quality firmware for SerDes PHY IP. You’ll help define architecture, drive features end-to-end, coordinate across cross-functional teams, and directly influence the design and usability of Qualcomm’s designs.

In this position, you will be:

Technical or project lead for SerDes firmware on a major IP program, working with a team (2–8 engineers) through planning, development, validation, and customer delivery

Owning the entire firmware lifecycle for SerDes PHY, from pre-silicon design through post-silicon validation and optimization

Gathering requirements, studying high-level designs, developing device interface functions, and turning small building blocks into higher-level firmware system design

Architecting and implementing embedded C/C++ firmware for hardware calibration, training algorithms, DSP adaptations, and link state management

Working with multi-functional teams — ASIC/digital design, digital verification, software, and systems engineering — to define detailed bring-up and validation requirements and meet performance goals

Communicating requirements and coordinating execution across multiple teams and sites

Translating bring-up and validation requirements into efficient C/C++ firmware code and well-structured software organization

Translating protocol specifications (e.g. PCIe, Ethernet, CXL, UCIe) or custom system-level requirements into internal firmware architecture and documentation

Developing test and debug capabilities that help guide hardware design decisions for future product iterations

Debugging complex lab and field issues in conjunction with hardware, applications, and validation teams, and driving low-level SW, silicon, and HW issues to root cause and closure

Driving multi-functional teams and partners to address integration and bring-up challenges, ensuring chips are seamlessly brought up, validated, tested, and meet product and business requirements

Planning and developing test cases that improve reliability and release quality for internal and external stakeholders, and ensuring they run continuously in regression

Working with external vendors and customers to ensure requirements are met and releases are of high quality

Driving and collaborating across functions to define FW milestones, plan sprints, close tickets, and deliver reliable, high-quality features

Implementing industry best practices and documenting firmware and hardware design specifications and decisions

Mentoring junior engineers, promoting team building, and driving continuous improvement in processes and techniques

Demonstrating full ownership of assigned systems/components, managing timelines and resolving project challenges to meet program timing

Staying current with advancements in the semiconductor industry and incorporating relevant innovations into our processes

Supporting development and silicon bring-up across Qualcomm teams and other sites

Example Problems You’ll Solve

Mentoring a junior engineer through a hard-to-reproduce PHY calibration bug seen in customer silicon

Developing architecture and state machines to handle multi-lane synchronization or adaptive equalization across dynamic conditions

Porting a high-level MATLAB or Python SerDes calibration algorithm to optimized fixed-point firmware

Creating a SerDes diagnostics framework accessible via both SDK and GUI

Using simulation environments, EDA tool integration, and FPGA emulation to validate FW behavior before tapeout

Building error monitoring and board/interface configuration APIs that make link health observable to SoC software teams

Standing up a regression suite that catches link-training regressions before a customer release ships

Working with IP hardware architects to influence future revisions based on field debug learnings

What We’re Looking For

BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or a related field

7+ years of experience in embedded C/C++ firmware development for hardware IP or SoCs, with strong proficiency in C/C++ and Python

Hands-on experience with embedded architectures such as ARM, RISC-V, or MIPS, and with low-level programming on bare metal, RTOS, BIOS/UEFI firmware, Linux kernel, or device drivers

Technical or team leadership experience in embedded software projects from spec to production

Deep understanding of microcontroller architecture (RISC-V a plus), memory-mapped registers, ISRs, and boot flows

Systems mindset and experience developing SW/FW to control analog, digital, and mixed-signal circuits

Experience with SerDes, Ethernet, PCIe, CXL, or D2D/UCIe/chiplet products and communication systems

Strong lab debug skills, working directly on silicon with scopes, JTAG debuggers, I2C/SPI tools, analyzers, and custom tooling, including bring-up and diagnostics of high-speed signals

Familiarity with industry-standard EDA tools and methodologies used for digital verification, and with HDLs such as Verilog and SystemVerilog

Familiarity with git and modern software development methodologies

Excellent organizational and communication skills, a willingness to learn, and the ability to collaborate across functions and geographies

Preferred Experience:

Knowledge of SerDes and high-speed IO standards (PCIe, Ethernet, UCIe, CXL, etc.)

Experience with calibration algorithms, signal conditioning, and adaptive feedback control in hardware

Experience in silicon bring-up and post-silicon debug

Experience in pre-silicon firmware development (DV, emulation, etc.)

Knowledge of RTOS or bare-metal FW architectures, including embedded Linux development, Buildroot/Yocto, and RTOSes such as Zephyr and FreeRTOS

Knowledge of peripherals and protocols such as 1G/10G Ethernet, DDR, I2C, SPI/QSPI, MIPI/CSI, GMSL, A2B, I2S, TDM, LVDS, PCIe, USB, NVMe, and CAN

Experience developing drivers for multiple devices at the PCB level to interact with whole systems

Experience creating error monitoring and board/interface configuration APIs

Hands-on lab validation experience with CPU, SoC, FPGA, MCU, and DSP components, including developing tests and debug tools

Experience working with FPGAs such as Xilinx, Zed, and MicroZed

Hardware hands-on and debugging experience, such as power, SI, and EMC validation and tuning

Scripting in Python, Bash, etc. for lab automation and testing

Familiarity with digital design concepts (Verilog/SystemVerilog), simulation, and DV flows

Exposure to the OSI model, especially the physical and data link layers

Understanding of signal processing concepts such as eye diagrams, jitter, BER, SNR, and CTLE/DFE/FFE

Experience with Jira, Agile/Scrum, and Confluence

Contributions to open source projects

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