LEC (Logic Equivalence Checking) CAD Engineer

@ Mirafra Technologies

View all jobs

Ontario

Full-time

Apply now

SIGNALS

Overview

Mirafra Technologies is hiring a LEC (Logic Equivalence Checking) CAD Engineer to develop and support formal equivalence methodologies that confirm functional correctness between RTL, synthesized netlists and physical designs in complex SoC development. The work covers owning LEC sign-off flows, enabling ECO flows, debugging non-equivalences, scripting automation and optimizing verification tools. The posting is a full-time role with no schedule, pay or work arrangement stated.

Responsibilities:

Own and maintain end-to-end LEC sign-off methodologies
Enable ECO flows for late-stage design modifications
Analyze and resolve non-equivalences and aborts
Write and maintain Tcl, Python, Perl or Shell automation
Optimize runtime and capacity of verification tools

Requirements summary:

Bachelor's or Master's in electrical engineering, computer science or related field
Dedicated hardware or EDA experience
Proficiency in Cadence Conformal (LEC/ECO)
Proficiency in Synopsys Formality

Tools & skills

Cadence Conformal Synopsys Formality Tcl Python Perl Shell

Source and dates

Source type not verified · apify-linkedin

Employer posting date: 2026-10-15
First seen by our source: 2026-11-11
Source record updated: 2026-11-11

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

Job details

Department	Engineering
Hours per week	40 (estimated)
Work setting	Office
Position	Mostly sitting
Physical demands	physical low · computer high
Languages	English
Education	Bachelor’s degree (required), Master’s degree (required)
Fields of study	Electrical Engineering, Computer Science

Summary and details written by AI from the posting; the employer’s posting is the authority.

Apply now

Mirafra Technologies

View all jobs

Field	Value
Open jobs on Jobsy	2

Job description

A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and physical designs in complex SoC (System on a Chip) development

Key Responsibilities

Flow Management: Own and maintain end-to-end LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows.

ECO Implementation: Enable Engineering Change Order (ECO) flows to ensure safe, correct late-stage design modifications.

Debugging & Root Cause: Analyze and resolve non-equivalences, aborts, and mismatches across design stages.

Automation: Write and maintain scripts and automation infrastructure using Tcl, Python, Perl, or Shell.

Tool Optimization: Optimize runtime, capacity, and scalability of verification tools while partnering with EDA vendors.

AI Enablement : Enable AI enabled tools and methodologies

Core Requirements

Tools Knowledge: Proficiency in industry-standard tools like Cadence Conformal (LEC/ECO) and Synopsys Formality.

Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related fields with dedicated hardware/EDA experience