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Posted 6 days ago

Principal Analog Circuit Designer

@ Ciena Canada ULC

Ottawa, Ontario

$142k–$226k/yrFull-time7+ years experience
Apply now
SIGNALS

Overview

Ciena Canada ULC is hiring a Principal Analog Circuit Designer to lead high-speed analog circuit design for coherent optical products. The work covers ADC circuits, precision analog control circuits, and clock generation through to GDSII. The posting states a pay range of C$141,700 to C$226,300 per year, plus a possible discretionary bonus.

Pay:

$141,700–$226,300 a year

Responsibilities:

  • Lead design of high-speed analog circuits in advanced CMOS or BiCMOS
  • Deliver ADC circuits interfacing with optical modulators and detectors
  • Design multi-phase clock generation and distribution through GDSII
  • Perform lab characterization of analog circuits from test chips to products

Requirements summary:

  • Master's degree in electrical, computer or applicable science
  • 7+ years of advanced CMOS or BiCMOS design experience
  • Demonstrated analog design at mm-wave frequencies
  • Proficiency with Cadence Virtuoso, Calibre, STAR-RC and MMSIM
  • Strong written and verbal English communication

Tools & skills

Benefits mentioned

Health insuranceDentalVisionRetirement planEmployee assistancePaid time offStock options
Source and dates

Employer career site / ATS feed · workday

Employer posting date
2026-11-01
First seen by our source
2026-10-08
Source record updated
2026-11-02

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

Job details

SenioritySenior
DepartmentEngineering
Experience7+ years
Hours per week40 (estimated)
Work settingOffice, Laboratory
PositionMostly sitting
Physical demandsphysical low · computer high
LanguagesEnglish
EducationMaster’s degree (required)
Fields of studyElectrical Engineering, Computer Engineering
Perks mentionedGenerous paid time off, Retirement plan, Performance bonus, Stock or equity, Wellness

Summary and details written by AI from the posting; the employer’s posting is the authority.

Ciena Canada ULC

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Job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.


Ciena’s WaveLogic family of products plays a critical role in enabling high-speed optical fiber transmission and advancing broadband connectivity solutions. This position contributes to the design and delivery of advanced analog circuits that power next-generation coherent optical technologies. The role is part of a team with a long history of innovation in high-speed data conversion and optical communication systems.


How you will make an impact:

• Lead design of advanced high-speed analog circuits in deep-submicron CMOS and/or BiCMOS technologies

• Deliver optical-line-facing ADC circuits interfacing with optical modulators and detectors within mixed-signal IP blocks

• Develop precision analog circuits for control and monitoring functions within integrated solutions

• Evaluate circuit topologies and recommend implementation approaches based on trade-off analysis

• Define and contribute to circuit requirement specifications in collaboration with cross-functional teams

• Design multi-phase clock generation and distribution circuits through to full GDSII delivery

• Perform lab-based characterization of analog circuits from test chips through full product implementation


The must haves:

• Education: Master’s degree in Electrical Engineering or Computer Engineering or other applicable scientific discipline

• 7+ years of experience contributing to designs in advanced CMOS and/or BiCMOS technology

• A highly motivated self-starter able to work independently and collaborate within a team environment

• Ability to address complex technical problems using methodical approaches

• Strong written and verbal communication skills in English

• Utilization of design tools such as Cadence Virtuoso, Calibre, STAR-RC, and MMSIM for analog design

• Demonstrated delivery of analog circuit designs at mm-wave frequencies


Nice to haves:

• Experience with 2.5D or 3D electromagnetic modeling tools such as HFSS or EMX

• Experience designing high-performance clock generation and distribution circuits

• Experience with mixed-signal design validation using advanced probing and test equipment

#LI-BS1

Pay Range:

The annual pay range for this position is C$141,700 - C$226,300.



Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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