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First seen by our source: 19 days ago

RTL Design Engineer - AI Tools

@ Mercor

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Toronto, Ontario

$100–$175/hr3+ years experience
Apply now
SIGNALS

Overview

Mercor is hiring an RTL Design Engineer on a remote, 40-hour-per-week contract of 3 or more months at $100 to $175 per hour. The role evaluates digital chip design workflows to improve AI model training, designs and verifies RTL components in Verilog and SystemVerilog, and uses LLM-based tools to speed up design and verification.

Pay:

$100–$175 an hour

Responsibilities:

  • Evaluate digital chip design workflows for AI model training
  • Design and verify RTL components in Verilog and SystemVerilog
  • Develop reusable verification components and testbench infrastructure
  • Collaborate with architecture and verification teams
  • Use LLM-based tools to accelerate design and verification

Requirements summary:

  • 3 to 10 years of digital RTL design or design verification
  • Strong Verilog, SystemVerilog and UVM proficiency
  • Understanding of FSMs, datapaths, pipelines and bus protocols
  • Experience with ASIC design flows and EDA tools
  • Clear design documentation and communication skills

Tools & skills

VerilogSystemVerilogUVMEDA tools
Source and dates

Source type not verified · manatal

Employer posting date
Not provided
First seen by our source
2026-10-18
Source record updated
2026-10-18

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

Job details

SeniorityMid level
DepartmentEngineering
Experience3+ years
Hours per week40
Travelair: none · ground: none
Work settingHome
PositionMostly sitting
Physical demandsphysical low · computer high
LanguagesEnglish

Summary and details written by AI from the posting; the employer’s posting is the authority.

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Mercor

Saved company profile

Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.

We connect human expertise with leading AI labs and enterprises to train frontier models.

Full company description

Mercor is defining the future of work. We connect human expertise with leading AI labs and enterprises to train frontier models.

LinkedIn followers
654,507
People associated on LinkedIn
5,250
Reported office locations
  • San Francisco, California 94105, US
Business categories
  • Employment
  • Software
  • Recruiting
  • Data Collection and Labeling
  • Artificial Intelligence (AI)
  • Machine Learning
Other recorded names
  • Mercor
Profile identifies a recruitment agency
Yes
Reported total investment
483,600,000

Currency and observation date were not supplied; this is not a current valuation or a funding round.

View all jobs Website

Mercor is defining the future of work. We connect human expertise with leading AI labs and enterprises to train frontier models.

FieldValue
IndustrySoftware Development
Company size51-200 employees
HeadquartersSan Francisco, California
Organization typePrivately Held
Year founded2023
Open jobs on Jobsy1,626
LinkedInView page
Job description

About the job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.

Position: RTL Design Engineers
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week

Role Responsibilities

  • Evaluate digital chip design workflows to enhance AI model training and evaluation.
  • Design and verify RTL components using Verilog/SystemVerilog.
  • Collaborate with architecture, verification, and implementation teams to improve model outputs.
  • Develop reusable verification components and testbench infrastructure.
  • Leverage LLM-based tools to accelerate chip design and verification processes.
  • Work independently and asynchronously to meet project deadlines.

Qualifications

Must-Have

  • 3–10 years of experience in digital RTL design or design verification.
  • Strong proficiency in Verilog/SystemVerilog and UVM.
  • Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
  • Experience with ASIC design flows and common EDA tools.
  • Ability to write clear design documentation and communicate technical tradeoffs.

Preferred

  • Knowledge of AMBA protocols (AXI, AHB, APB).
  • Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
  • Exposure to formal verification or SV/UVM-based design verification.

Start Date

  • Week of 04/23; applications reviewed on a rolling basis.

Compensation & Legal

  • Hourly contractor, Paid weekly.

Application Process (Takes 20–30 mins to complete)

  • Upload resume
  • AI interview based on your resume
  • Submit form

Resources & Support

  • For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
  • For any help or support, reach out to: [email protected]

PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.

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