Silicon Design Engineer

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THE ROLE:

This is an ASIC Verification Engineering role within the Security IP Team (SECIP). The role focuses on co-verification of embedded microprocessor subsystems and associated hardware accelerators in leading-edge SoCs. The ideal candidate will also contribute to firmware development initiatives supporting high-performance subsystems such as security policy management, cryptography, data compression, and high-throughput DMA. This is Junior Level position . New grad are allowed to apply .

THE PERSON:

The ideal candidate is a highly analytical engineer with strong problem-solving skills and attention to detail, capable of independently driving complex technical tasks to completion. They thrive in a collaborative environment, communicate effectively across hardware and firmware teams, and demonstrate a passion for building scalable, high-performance solutions in security-focused SoC environments. A proactive mindset and the ability to influence design and verification strategies are critical for success in this role. If this sounds like a role you are interested in, we welcome you to apply!

KEY RESPONSIBILITIES:

• Develop and verify embedded firmware for SoC secure boot and microprocessor-driven hardware acceleration services, including cryptography, compression, and DMA
• Perform hardware/firmware co-verification using UVM System Verilog, C-DPI, and FPGA-based prototyping platforms
• Define and maintain subsystem verification architecture, testbenches, and methodologies for embedded CPU and IP subsystems using AXI/AHB interfaces
• Collaborate on subsystem specification and influence hardware and firmware co-design, including developing abstracted performance models and evaluating architecture trade-offs
• Develop and execute block- and subsystem-level test plans using UVM randomized and C-DPI directed methodologies
• Build and maintain verification infrastructure, including UVCs, system response models, integration scripts, and build/run environments
• Drive verification closure, improve coverage metrics, and debug complex hardware/firmware interactions
• Interface with SoC integration and DV teams to support IP-level APIs, SoC-level validation, emulation, silicon bring-up, and debug

PREFERRED EXPERIENCE:

• Strong experience in ASIC firmware and hardware design and verification
• Proficiency in C, C++, Assembly, Verilog, System Verilog, and scripting languages such as Python, Perl, and Make
• Deep expertise in UVM and C-DPI methodologies
• Strong understanding of standard bus/interface protocols (AXI, AHB, AMBA)
• Experience with firmware development on commercial microprocessors and associated toolchains (compiler, assembler, debugger)
• Hands-on experience with ASIC verification tools, including simulation, linting, and power-aware verification

ACADEMIC CREDENTIALS:

Bachelor’s degree in electrical or computer engineering required; master’s or PhD preferred

LOCATION: Markham, Ottawa

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.