Posted 22 days ago
Staff FPGA Engineer
@ Cognichip
Toronto, Ontario
SIGNALS
Overview
Cognichip is hiring a Staff FPGA Design Engineer to fuse chip design expertise with machine learning in its AI chip design assistant team. The work centres on RTL design, EDA workflows, dataset creation and UVM verification in a hybrid role based in Toronto, with four office days and one remote day per week.
Responsibilities:
- Serve as chip design domain expert for AI design assistants
- Architect EDA workflows from spec to bitstream
- Drive agentic AI systems that author RTL and manage IP
- Design and synthesize complex RTL and verification datasets
- Define UVM verification standards and coverage models
Requirements summary:
- Master's in computer science, electrical engineering or related field
- 10 to 15 years of RTL design or design and verification
- Deep AMD/Xilinx and Altera/Intel FPGA tool expertise
- Knowledge of AXI, Ethernet, PCIe, DDR5 and NoC protocols
- Proficiency in SystemVerilog, Python and TCL
Tools & skills
Source and dates
Source type not verified · apify-linkedin
- Employer posting date
- 2026-10-22
- First seen by our source
- 2026-11-14
- Source record updated
- 2026-11-14
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Engineering |
| Experience | 10+ years |
| Hours per week | 40 (estimated) |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Master’s degree (required) |
| Fields of study | Computer Science, Electrical Engineering |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Cognichip
| Field | Value |
|---|---|
| Open jobs on Jobsy | 4 |
Job description
Job Title
Staff Chip Design Engineer - FPGA
Job Description
Staff FPGA Design Engineer
Why This Matters At Cognichip, we’re not just building AI—we’re redefining what’s possible at the nexus of silicon design and machine learning. As a Staff FPGA Design Engineer, you will fuse chip design expertise with cutting-edge ML to create the intelligent, end-to-end silicon design flows. If you thrive on pushing the envelope of the possible and translating cutting-edge ideas into production-grade systems, this is your stage.
What You'll Do
The following items are not required but are great bonuses:
We’re a fast-moving AI startup with a collaborative, high-trust culture. You’ll work with top-tier engineers, scientists, and builders—solving hard problems that sit at the intersection of cloud computing, AI, and chip design. We value technical excellence, ownership, and the freedom to experiment. If you’re excited to build the future of engineering, you’ll feel right at home.
Logistics
This position is available in Toronto. We believe a mindmeld between engineers and scientists leads to our professional growth and to great products; we have a hybrid schedule with four days in office, one day remote.
How To Apply
Don’t meet every single requirement? Feel over-qualified? That’s okay—if you're excited about our mission, we’d still love to hear from you. We are growing fast and need a world class team of various experience levels.
Staff Chip Design Engineer - FPGA
Job Description
Staff FPGA Design Engineer
Why This Matters At Cognichip, we’re not just building AI—we’re redefining what’s possible at the nexus of silicon design and machine learning. As a Staff FPGA Design Engineer, you will fuse chip design expertise with cutting-edge ML to create the intelligent, end-to-end silicon design flows. If you thrive on pushing the envelope of the possible and translating cutting-edge ideas into production-grade systems, this is your stage.
What You'll Do
- Serve as the domain expert, embedding chip design intuition into a team creating AI chip design assistants
- Architect modern EDA workflows, from spec to bitstream
- Drive the development of agentic AI systems capable of authoring syntactically and semantically correct RTL, manage IP integration, and constructing processor-based designs
- Create an ecosystem of libraries, tools, agents, workflows, and benchmarks to increase design velocity
- Design and synthesize high-quality, complex datasets (RTL, IP, constraints, failure modes) to train models on hardware physics and logic
- Define rigorous verification standards and guide the agent in generating robust UVM testbenches, assertions and coverage models to ensure generated designs are correct-by-construction
- Masters in Computer Science, Electrical Engineering, or a closely related field
- 10-15 years of experience in RTL design, or a combination of design and verification
- Deep expertise with AMD/Xilinx (Vivado, Vitis) and Altera/Intel (Quartus) ecosystems, including SoC and complex IP integrations
- Knowledge of industry-standard communication protocols (AXI, Ethernet, PCIe, DDR5, SPI, I2C, NoC, etc)
- Proficiency in SystemVerilog, Python, and TCL
- Excellent written and verbal communication skills, especially to convey chip design knowledge to software engineers and AI scientists
- Comfortable working in a dynamic, research-heavy AI-oriented startup environment
The following items are not required but are great bonuses:
- Personal projects showcasing innovation, creativity, and continuous learning
- Knowledge of open-source tools and contribution practices (Verilator, CocoTB, Yosys, OpenSTA, etc)
- Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design, etc)
- Demonstrated coursework or project experience in machine learning and/or deep learning
We’re a fast-moving AI startup with a collaborative, high-trust culture. You’ll work with top-tier engineers, scientists, and builders—solving hard problems that sit at the intersection of cloud computing, AI, and chip design. We value technical excellence, ownership, and the freedom to experiment. If you’re excited to build the future of engineering, you’ll feel right at home.
Logistics
This position is available in Toronto. We believe a mindmeld between engineers and scientists leads to our professional growth and to great products; we have a hybrid schedule with four days in office, one day remote.
How To Apply
Don’t meet every single requirement? Feel over-qualified? That’s okay—if you're excited about our mission, we’d still love to hear from you. We are growing fast and need a world class team of various experience levels.
Journal
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