Posted last month
CPU Micro-Architect / RTL (Lead & IC Engineers)
@ NUVACORE
Canada
Overview
NUVACORE is hiring CPU Micro-Architect and RTL engineers, both leads and individual contributors, to design a new general-purpose CPU core for AI infrastructure and agentic computing. The work covers micro-architecture specification, RTL development, verification support, performance exploration and physical design. Full-time.
Responsibilities:
- Develop micro-architecture and write detailed CPU specifications
- Design and refine RTL for power, performance, area and timing goals
- Support testbench development, formal methods and simulation/emulation
- Explore performance strategies with the performance architecture team
- Work with physical design to meet timing, power, area and reliability goals
Requirements summary:
- BS or MS with 15+ years (leads) or 7+ years (ICs) in CPU design
- Experience coding and debugging in Verilog and simulation
- Solid understanding of logic and physical design impacts on timing, power and area
- Experience with RISC-V, ARM64 or x86 ISA and micro-architectural impacts
Tools & skills
Source and dates
Employer career site / ATS feed · lever
- Employer posting date
- 2026-09-22
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-10-26
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Engineering |
| Experience | 7+ years |
| Hours per week | 40 (estimated) |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Education | Bachelor’s degree (required), Master’s degree (preferred) |
Summary and details written by AI from the posting; the employer’s posting is the authority.
NUVACORE
Saved company profile
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
NUVACORE is building a new class of CPU for the AI era, designed for maximum performance, efficiency, and scale.
Full company description
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
- LinkedIn followers
- 5,838
- People associated on LinkedIn
- 82
- Reported office locations
- 5201 Great America Pkwy, Suite 215, San Jose, California 95054, US
- 5001 Plaza on the Lk, Suite 320, Austin, TX 78746, US
- 125 Commerce Valley Dr W, Suite 600, Markham, Ontario L3T 7W4, CA
- Other recorded names
- NUVACORE
- Profile identifies a recruitment agency
- No
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
| Field | Value |
|---|---|
| Industry | Technology, Information and Internet |
| Company size | 51-200 employees |
| Headquarters | San Jose, California |
| Organization type | Privately Held |
| Year founded | 2026 |
| Open jobs on Jobsy | 9 |
| View page |
At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past.As engineers within the CPU team and as leads of CPU units (fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and multi-level cache subsystem), you will be writing specifications and developing RTL for the CPU which targets and delivers industry leading power, performance, and area.
THE ROLE
As a CPU Micro-Architect/RTL Engineer, you will participate in the following:
Micro-architecture development and specification - starting from a performance driven design strategy, you will work with our performance modeling team and study early micro-architectures and converge on a design captured in a detailed specification. Critical understanding of the various pipelines and intra-unit communication will be necessary to build a clean yet performant design.
RTL design - develop and refine RTL which targets the power, performance, area and timing goals. A solid understanding of the modern Verilog standards is a plus, enabling you to write RTL which is flexible and robust, configurable, and scalable.
Verification - assist the verification team in all forms of CPU verification used, such as testbench development, formal methods, and simulation/emulation for formal verification
Performance exploration and correlation - explore high-performance strategies and work with the performance architecture and verification team to verify that the RTL meets targeted performance.
Physical design - work with the PD engineering team to implement and verify the physical design meets the goals. Be able to iterate and refine the RTL design. Incorporate improvements for timing, power, area, DFT, and reliability.
REQUIREMENTS — MUST TO HAVE
BS or MS with 15+ (leads) and 7+ (ICs) years experience in high-performance, low-power CPU design
Experience with coding in Verilog, debugging, simulation, ideally with experience driving modern AI Tools to assist in RTL coding
Solid understanding of logic and physical design and the impacts on timing, power, and area
Experience with RISC-V or ARM64 or x86 ISA and their impacts on CPU micro-architectural choices
REQUIREMENTS — NICE TO HAVE
Expertise in one or more of the following areas: instruction fetch, branch prediction; instruction decoding, scheduling and register renaming; out-of-order execution; integer and floating point execution; load/store execution; prefetching; cache and memory subsystems; translation and memory management; memory coherence and ordering; power and thermal management; and clocking / reset design
Strong background in low power microarchitecture and high-performance design techniques, with a proven track record of execution on multiple CPU programs and products
Experience in C, C++, and other languages such as Perl or Python
The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.
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