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CPU Performance Modeling (Lead & ICs)
@ NUVACORE
Canada
Overview
NUVACORE is hiring a CPU Performance Modeling Lead, and senior individual contributors, to own its cycle-accurate CPU performance simulator and drive architectural decisions from pathfinding through tape-out and post-silicon correlation. The role covers microarchitectural exploration, model-to-RTL correlation, cross-team collaboration and mentoring. The posting requires an MS (PhD preferred) and 20+ years for Lead or 8+ years for ICs in CPU microarchitecture and performance engineering.
Responsibilities:
- Own cycle-accurate CPU performance simulator and roadmap
- Lead microarchitectural exploration across frontend, OOO and memory
- Drive model-to-RTL and post-silicon correlation
- Collaborate with design, verification and compiler teams
- Mentor performance engineers and provide technical leadership
Requirements summary:
- MS in computer architecture or related field (PhD preferred)
- 20+ years (Lead) or 8+ years (ICs) in CPU performance engineering
- Hands-on experience with cycle-accurate C++ simulators such as gem5
- Deep expertise in branch prediction, OOO, memory or prefetchers
- Strong C++, Python or Perl and assembly skills
- Track record from pathfinding through silicon
Tools & skills
Source and dates
Employer career site / ATS feed · lever
- Employer posting date
- 2026-09-22
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-10-26
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Lead |
| Department | Engineering |
| Experience | 8+ years |
| Manages people | Yes |
| Hours per week | 40 (estimated) |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Master’s degree (required), Doctorate (preferred) |
| Fields of study | Computer Architecture, Computer Engineering |
Summary and details written by AI from the posting; the employer’s posting is the authority.
NUVACORE
Saved company profile
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
NUVACORE is building a new class of CPU for the AI era, designed for maximum performance, efficiency, and scale.
Full company description
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
- LinkedIn followers
- 5,838
- People associated on LinkedIn
- 82
- Reported office locations
- 5201 Great America Pkwy, Suite 215, San Jose, California 95054, US
- 5001 Plaza on the Lk, Suite 320, Austin, TX 78746, US
- 125 Commerce Valley Dr W, Suite 600, Markham, Ontario L3T 7W4, CA
- Other recorded names
- NUVACORE
- Profile identifies a recruitment agency
- No
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
| Field | Value |
|---|---|
| Industry | Technology, Information and Internet |
| Company size | 51-200 employees |
| Headquarters | San Jose, California |
| Organization type | Privately Held |
| Year founded | 2026 |
| Open jobs on Jobsy | 9 |
| View page |
At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. As our CPU Performance Modeling Lead, you will own the performance modeling infrastructure and methodology that drives every architectural decision we make — from early pathfinding through tape-out and post-silicon correlation.
THE ROLE
Design, develop and own Nuvacore’s cycle-accurate CPU performance simulator — its architecture, fidelity, and long-term roadmap — as the authoritative reference model for the design team.
Lead microarchitectural exploration across all major CPU domains: frontend (fetch, decode, branch prediction), out-of-order engine (rename, dispatch, execution), and memory subsystem (caches, prefetchers, TLBs, coherence).
Drive model-to-RTL correlation through all execution phases; own debug and resolution of performance miscorrelation between the performance model, RTL simulation, and post-silicon results.
Collaborate closely with design, verification, compiler, and system software teams to align architecture decisions with implementation constraints and software stack realities.
Mentor engineers across the performance team; provide technical leadership on modeling methodology, simulation infrastructure, and analysis tooling.
Contribute to IP development through patents and, where applicable, external publication
REQUIREMENTS — MUST HAVE
MS in Computer Architecture, Computer Engineering, or related field (PhD preferred).
20+ years (Lead) or 8+ years (ICs) in CPU microarchitecture and/or performance engineering.
20+ years (Lead) or 8+ years (ICs) of hands-on experience with cycle-accurate C++ CPU performance simulators (e.g. gem5 or equivalent in-house tools).
Deep expertise in at least one of: branch prediction, fetch/decode, rename/dispatch, OOO execution, memory subsystem, or prefetchers.
Strong C++ and Python / Perl skills; ability to write and analyze assembly for microarchitectural test cases.
Proven track record driving performance from pathfinding through silicon (RTL correlation and/or post-Si debug).
Experience in RISC-V or ARM64 or x86 ISA.
Strong track record in identifying ideas to improve power/performance/area (PPA) of CPUs.
REQUIREMENTS — NICE TO HAVE
Experience with compiler optimizations and hardware/software co-design.
Published work or filed patents in CPU performance or microarchitecture.
Prior principal-level role at a CPU design organization.
The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.
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