Posted 6 months ago
DV - Staff (+) Verification Engineer - AMS modeling
@ Eliyan
Canada
Overview
Eliyan is hiring a Staff Verification Engineer for AMS modeling of chiplet PHYs, with a focus on SerDes. The role is hands-on: writing RNM AMS SystemVerilog models from schematics and verifying them with analog and design teams. Work is onsite Monday to Friday, with excellent benefits described.
Responsibilities:
- Develop and execute RNM AMS models for PHYs
- Ensure models reflect schematics
- Write and debug SystemVerilog/UVM test cases
- Collaborate with design team on design quality
- Understand analog blocks
Requirements summary:
- 5+ years relevant experience
- BS in EE or related field
- Deep analog design expertise
- SystemVerilog, test environment and assertion coding
- Experience verifying mixed-signal IPs
- Formal verification with JasperGold or vc-formal (preferred)
Tools & skills
Source and dates
Employer career site / ATS feed · lever
- Employer posting date
- 2026-05-20
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-10-15
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Software development |
| Experience | 5+ years |
| Hours per week | 40 |
| Schedule | day |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Bachelor’s degree (required) |
| Fields of study | Electrical Engineering |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Eliyan
Saved company profile
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
Accelerating a Smarter Future by Revolutionizing Chiplet-based Systems
Full company description
Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.
- LinkedIn followers
- 5,761
- People associated on LinkedIn
- 82
- Reported office locations
- Santa Clara, US
- Business categories
- Electronics
- Semiconductor
- Manufacturing
- Other recorded names
- Eliyan
- Eliyan Corporation
- Profile identifies a recruitment agency
- No
- Reported total investment
- 150,000,000
Currency and observation date were not supplied; this is not a current valuation or a funding round.
Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.
| Field | Value |
|---|---|
| Industry | Semiconductor Manufacturing |
| Company size | 11-50 employees |
| Headquarters | Santa Clara |
| Organization type | Privately Held |
| Year founded | 2021 |
| Open jobs on Jobsy | 5 |
| View page |
Join the leading chiplet startup! As an Eliyan Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art AMS systemVerilog models (RNM) for best-in-class PHYs. You will own verification of AMS SystemVerilog models. This is a hands-on technical role. You'll work with analog team, look at schematics and write the RNM models. We offer a fun work environment with excellent benefits. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities:
- Develop and execute RNM AMS model for best in class PHYs.
- Make sure the quality of models reflects schemetics.
- Write and debug SystemVerilog/UVM compliant test cases
- Collaborate with design team to ensure design quality
- Expertise to understand analog blocks.
Required Qualifications:
- 5+yrs relevant experience
- BS in EE or related field.
- Deep analog design expertise
- Knowledge of SystemVerilog, test environment and assertion coding
- Experience in verifying mixed signal IPs
Preferred Qualifications:
- Experience with Formal verification with Jasper Gold or vc-formal
- Python/Perl/Tcl scripting for design verification
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