DV - Staff Verification Engineer - Serdes
CanadaOn-siteFull Time
E
Eliyan
7+ YOECandidates need at least 7 years of verification experience, including 4 years in PHY or high-speed interfaces, with deep SerDes/PCIe PHY expertise and strong UVM/SystemVerilog skills. Eliyan also values experience verifying mixed-signal IP and integrating VIPs.
SystemVerilog, UVM, Jasper Gold, vc-formal, Python, Perl