Posted 7 months ago
DV - Staff Verification Engineer - Serdes
@ Eliyan
Canada
Overview
Eliyan is hiring a Staff Design Engineer to lead verification of SerDes and other PHYs for chiplet-based systems. The role covers verification planning, UVM/SystemVerilog testbenches and technical mentoring of junior engineers. The posting requires onsite work Monday to Friday and a security clearance (DV).
Responsibilities:
- Develop and execute verification plans for SerDes, PHYs and DSP blocks
- Create and maintain SystemVerilog/UVM verification environments
- Write and debug UVM test cases for block and chip level
- Lead verification of TX/RX equalization and CDR
- Mentor junior verification engineers
Requirements summary:
- BS plus 7 years of verification experience
- 4+ years in PHY or high-speed interfaces
- Deep SerDes/PCIe PHY verification expertise
- Strong UVM/SystemVerilog and assertion coding skills
- Experience verifying mixed-signal IPs and integrating VIPs
Tools & skills
Source and dates
Employer career site / ATS feed · lever
- Employer posting date
- 2026-04-07
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-10-15
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Engineering |
| Experience | 7+ years |
| Hours per week | 40 (estimated) |
| Schedule | day |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Bachelor’s degree (required) |
| Security clearance | Other clearance |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Eliyan
Saved company profile
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
Accelerating a Smarter Future by Revolutionizing Chiplet-based Systems
Full company description
Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.
- LinkedIn followers
- 5,761
- People associated on LinkedIn
- 82
- Reported office locations
- Santa Clara, US
- Business categories
- Electronics
- Semiconductor
- Manufacturing
- Other recorded names
- Eliyan
- Eliyan Corporation
- Profile identifies a recruitment agency
- No
- Reported total investment
- 150,000,000
Currency and observation date were not supplied; this is not a current valuation or a funding round.
Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.
| Field | Value |
|---|---|
| Industry | Semiconductor Manufacturing |
| Company size | 11-50 employees |
| Headquarters | Santa Clara |
| Organization type | Privately Held |
| Year founded | 2021 |
| Open jobs on Jobsy | 5 |
| View page |
Join the leading chiplet startup! As an Eliyan Staff Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You'll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities:
- Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.
- Create and maintain SystemVerilog/UVM-based verification environments
- Write and debug SystemVerilog/UVM compliant test cases for block and chip level
- Maintain regression environments
- Collaborate with design team to ensure design quality
- Develop, maintain, and track various test plan items and progress towards RTL freeze
- Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
- Integration of 3rd party VIPs and coordinate feature/bug tracking requests
- As a technical leader, mentor junior verification engineers
- GLS simulation for functional verification and power calculations
Required Qualifications:
- BS + 7 years of verification experience with 4+ years in PHY or high-speed interfaces
- Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDR
- Strong expertise in UVM/SystemVerilog, test environment and assertion coding
- Experience in verifying mixed signal IPs as well as integration of VIPs
Preferred Qualifications:
- 10+ years with demonstrated verification technical leadership
- Experience with Formal verification with Jasper Gold or vc-formal
- Experience with GLS simulations
- Python/Perl/Tcl scripting for design verification
- Proficiency in 3rd party tools for regression management and coverage analysis
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