Posted 8 days ago
RTL Design Engineer
@ HCLTech
Canada
Overview
HCLTech is hiring an RTL Design Engineer in Canada to develop Verilog/SystemVerilog RTL and PCIe Gen3/Gen4/Gen5 designs. The role covers micro-architecture definition, RTL implementation, debugging and performance optimization, working with cross-functional teams across the design lifecycle. Full-time; location is Canada.
Responsibilities:
- Develop and implement RTL designs in Verilog/SystemVerilog
- Work on PCIe Gen3/Gen4/Gen5 design and verification
- Contribute to micro-architecture definition and RTL implementation
- Perform debugging, validation and performance optimization
- Collaborate with cross-functional teams
Requirements summary:
- Hands-on RTL design in Verilog/SystemVerilog
- Hands-on PCIe protocol experience (Gen3/Gen4/Gen5 preferred)
- Understanding of FSM, pipelining, CDC, reset architecture, synchronizers, low-power design
- Micro-architecture and RTL implementation experience
- Knowledge of synthesis constraints and timing
- Familiarity with Lint, CDC, STA and low-power verification
Tools & skills
Source and dates
Source type not verified · apify-linkedin
- Employer posting date
- 2026-11-02
- First seen by our source
- 2026-11-11
- Source record updated
- 2026-11-11
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Hours per week | 40 (estimated) |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
Summary and details written by AI from the posting; the employer’s posting is the authority.
HCLTech
| Field | Value |
|---|---|
| Open jobs on Jobsy | 21 |
We're looking for a talented RTL Design Engineer with strong expertise in Verilog/SystemVerilog and PCIe protocol design/verification to join our growing team.
If you have a passion for digital design, micro-architecture development, and solving complex hardware challenges, we'd love to connect with you!
🔹 Key Responsibilities:
- Develop and implement RTL designs using Verilog/SystemVerilog.
- Work on PCIe (Gen3/Gen4/Gen5) design and verification activities.
- Contribute to micro-architecture definition and RTL implementation.
- Perform debugging, validation, and performance optimization.
- Collaborate with cross-functional teams throughout the design lifecycle.
🔹 Required Skills:
✅ Strong hands-on experience in RTL Design using Verilog/SystemVerilog
✅ Hands-on experience with PCIe protocols (Gen3/Gen4/Gen5 preferred)
✅ Solid understanding of digital design fundamentals:
- FSM Design
- Pipelining
- Clock Domain Crossing (CDC)
- Reset Architecture
- Synchronizers
- Low-Power Design Concepts
✅ Experience in micro-architecture development and RTL implementation
✅ Knowledge of synthesis constraints and timing concepts
✅ Familiarity with Lint, CDC, STA, and low-power verification methodologies
✅ Strong debugging and problem-solving skills
📍 Location: Canada
If you're interested or know someone who would be a great fit, please reach out directly or send your updated resume.
#RTLDesign #Verilog #SystemVerilog #PCIe #Semiconductor #VLSI #ASICDesign #HardwareEngineering #DigitalDesign #Hiring #CanadaJobs #HCLTech #TechCareers
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