Posted 5 days ago
Senior ASIC Design Engineer - Client IP
@ Ciena Canada ULC
Ottawa, Ontario
Overview
Ciena Canada ULC is hiring a Senior ASIC Design Engineer to design power- and area-optimized digital functional blocks for its Wavelogic optical transmission products. The role covers RTL design, implementation specifications, timing constraints, synthesis reviews and lab validation. Full-time, with a stated pay range of $111,900 - $178,700 CAD per year.
Pay:
$111,900–$178,700 a year
Responsibilities:
- Design power and area optimized digital functional blocks
- Write and integrate RTL code and implementation specifications
- Debug code through simulation and regression verification
- Craft timing constraints and review synthesis and timing reports
- Participate in lab validation of products and prototypes
Requirements summary:
- BEng/BSc or MEng/MSc in electrical, computer or other applicable science
- 5+ years SystemVerilog design experience
- 5+ years digital synthesis, STA, timing closure and clock crossings
- Familiarity with digital and formal verification methods
- Good understanding of timing, power and area trade-offs
- Excellent English communication skills
Tools & skills
Benefits mentioned
Source and dates
Employer career site / ATS feed · workday
- Employer posting date
- 2026-11-01
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-11-02
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Engineering |
| Experience | 5+ years |
| Hours per week | 40 (estimated) |
| Work setting | Office, Laboratory |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Bachelor’s degree (required), Master’s degree (preferred) |
| Fields of study | Electrical engineering, Computer engineering |
| Perks mentioned | Generous paid time off, Retirement plan, Performance bonus, Stock or equity, Wellness |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Ciena Canada ULC
| Field | Value |
|---|---|
| Open jobs on Jobsy | 75 |
As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.
How You Will Contribute:
The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects.
Your role as a senior digital design engineer will be to propose innovative solutions, in order to design power and area optimized functional blocks for the Wavelogic family of products.
- As a senior digital design engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
- You will produce an implementation specification document and have it reviewed by your team, architects, analog designers if applicable
- You are accountable for the creation and integration of new and existing RTL code, algorithms and functions
- You are held responsible for designer testing of your code as well as debugging of your code during simulation and regression verification
- You will assist the verification team in determining coverage and provide design assertions and waivers as needed
- You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
- You will be involved in lab validation of the product and its prototype if applicable
- You are expected to report on status updates on a regular basis
The Must Haves:
- Electrical or computer engineering, or other applicable scientific degree at the BEng/BSc or MEng/MSc level
- Experience: 5+ years using System Verilog for design
- Experience: 5+ years running digital design synthesis, STA, timing closure and asynchronous clock crossings
- A highly motivated self-starter, able to work independently, while being a team player
- Ability to methodically solve complex technical problems
- Excellent organization, written and oral (English) communication skills
- Familiarity with digital (including formal) verification methods
- Good understanding of timing/power/area analysis and trade-offs
Assets:
- Experience with digital silicon design backend process
- Experience with digital design for low power
- Experience with standards and protocols such as OTN/FlexO/B100G, Ethernet (100GE+)
- Experience with using GIT for source code management and revision tracking
- Experience with using Jira for schedule planning, assignment tracking and bug reporting
- Familiarity with programming languages such as Python, Make, bash.
The annual pay range for this position is $111,900 - $178,700 CAD.
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Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
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