Posted 2 months ago
CPU Architecture Verification Engineer
@ NUVACORE
Markham, Ontario
Overview
NUVACORE is hiring CPU Architecture Verification Engineers at Senior and Principal levels to prove its new general-purpose CPU is architecturally correct. The work is design verification: building stimulus, checkers and co-simulation against a golden reference model, and closing coverage before silicon.
Responsibilities:
- Drive verification scope, strategy and test plans for architectural correctness
- Build and scale verification environments with golden model co-simulation
- Generate assembly and random instruction sequence stimulus for corner cases
- Define functional coverage and close coverage against the test plan
- Root-cause mismatches across RTL, model and specification with architects
Requirements summary:
- Degree in electrical/computer engineering or computer science, or equivalent experience
- 4+ years (Senior) or 15+ years (Principal) of design verification
- Strong CPU architecture and microarchitecture knowledge
- Proficiency in C/C++/Rust or SystemVerilog, plus Python
- Experience writing and debugging assembly tests for CPU verification
Tools & skills
Source and dates
Employer career site / ATS feed · lever
- Employer posting date
- 2026-09-08
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-10-26
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Software development |
| Experience | 4+ years |
| Hours per week | 40 (estimated) |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Bachelor’s degree (required) |
| Fields of study | Electrical Engineering, Computer Engineering, Computer Science |
Summary and details written by AI from the posting; the employer’s posting is the authority.
NUVACORE
Saved company profile
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
NUVACORE is building a new class of CPU for the AI era, designed for maximum performance, efficiency, and scale.
Full company description
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
- LinkedIn followers
- 5,838
- People associated on LinkedIn
- 82
- Reported office locations
- 5201 Great America Pkwy, Suite 215, San Jose, California 95054, US
- 5001 Plaza on the Lk, Suite 320, Austin, TX 78746, US
- 125 Commerce Valley Dr W, Suite 600, Markham, Ontario L3T 7W4, CA
- Other recorded names
- NUVACORE
- Profile identifies a recruitment agency
- No
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
| Field | Value |
|---|---|
| Industry | Technology, Information and Internet |
| Company size | 51-200 employees |
| Headquarters | San Jose, California |
| Organization type | Privately Held |
| Year founded | 2026 |
| Open jobs on Jobsy | 9 |
| View page |
At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification — checking the CPU's behavior and architectural state against the architecture specification and a golden reference model — building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.
THE ROLE
Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.
Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end.
Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.
REQUIREMENTS — MUST TO HAVE
Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Strong knowledge of CPU architecture and micro-architecture — the instruction set, architectural state, exceptions, and privilege model — with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).
Hands-on functional verification: test plans, testbenches, checkers, and coverage.
Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
Experience writing and debugging tests in assembly for CPU verification.
REQUIREMENTS — NICE TO HAVE
Architectural / instruction-set verification against a golden reference model.
Random instruction sequence (RIS) stimulus generation.
Exceptions, interrupts, privilege levels, and virtualization.
Constrained-random verification and coverage-driven closure.
Assertions and formal verification.
Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
Journal
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