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Intermediate/Senior Digital IC Design Engineer

@ INNOSILICON

Ottawa, Ontario

Full-time5+ years experience
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SIGNALS

Responsibilities:

  • Design specification : Help write block-level design specifications, run system-level simulations, and support chip-level architecture definition and…
  • Implementation : Develop RTL in Verilog and take blocks through lint, clock domain crossing (CDC) analysis, synthesis, static timing analysis, timing closure,…
  • Verification: Work with the verification team on test planning and execution, debug block- and system-level simulations, and support formal verification.
  • Flow and methodology: Help develop and improve the design flows and methods used across our interdisciplinary R&D group.
  • Validation and production: Work with the validation and production teams to create test plans and test vectors that ensure product quality and robustness.

Requirements summary:

  • Proactive, curious and eager to learn, great attention to details, positive, and great team work
  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • 5 years of relevant digital FPGA/ASIC/IC design experience
  • Significant experience with RTL coding in Verilog/SystemVerilog
  • Significant experience with standard ASIC software tools (lint, clock domain crossing analysis, timing constraints, synthesis, simulation, logical equivalence checking, DFT, static timing…
  • Strong knowledge of Python scripting, Linux/Unix environment, and basic C/C++ programming

Tools & skills

Source and dates

Source type not verified · apify-linkedin

Employer posting date
2026-11-09
First seen by our source
2026-11-10
Source record updated
2026-11-10

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

INNOSILICON

Job description

Innosilicon is seeking to hire an Intermediate/Senior Digital IC Design Engineer to join our Inter-connectivity Memory Business Unit. The successful candidate will work with our experienced global engineering team developing market-leading SerDes IP products. We look forward to welcoming talented engineers on our journey.

Responsibilities

  • Design specification: Help write block-level design specifications, run system-level simulations, and support chip-level architecture definition and documentation.
  • Implementation: Develop RTL in Verilog and take blocks through lint, clock domain crossing (CDC) analysis, synthesis, static timing analysis, timing closure, and top-level integration. Support DFT tasks.
  • Verification: Work with the verification team on test planning and execution, debug block- and system-level simulations, and support formal verification.
  • Flow and methodology: Help develop and improve the design flows and methods used across our interdisciplinary R&D group.
  • Validation and production: Work with the validation and production teams to create test plans and test vectors that ensure product quality and robustness.

Qualifications

  • Proactive, curious and eager to learn, great attention to details, positive, and great team work
  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • 5 years of relevant digital FPGA/ASIC/IC design experience
  • Significant experience with RTL coding in Verilog/SystemVerilog
  • Significant experience with standard ASIC software tools (lint, clock domain crossing analysis, timing constraints, synthesis, simulation, logical equivalence checking, DFT, static timing analysis)
  • Strong knowledge of Python scripting, Linux/Unix environment, and basic C/C++ programming
  • Strong knowledge of PCIe, Ethernet
  • Thorough understanding of ASIC design flow
  • Design-for-verification experience or understanding (assertion-based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
  • Self-starter and fast learner with excellent interpersonal skills
  • Track record of driving technical solutions across organizational boundaries and multiple technical disciplines
  • Proficiency in Chinese would be considered an asset

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