Posted last month
Lead SOC Architect
@ NUVACORE
Canada
Overview
NUVACORE is hiring a Lead SoC Architect to own the system-on-chip architecture around its new general-purpose CPU core for AI infrastructure. The role sets architectural direction for fabric, memory, I/O, power and security, and drives trade-offs through design, verification, physical design and software. The posting states full-time employment and a requirement of 20+ years of SoC or system architecture experience.
Responsibilities:
- Own overall SoC architecture: fabric, caches, I/O, power and memory
- Architect coherent fabric and cache coherency protocol
- Architect PCIe/CXL I/O and DDR/LPDDR memory subsystems
- Author architecture specs and drive reviews to closure
- Support silicon bring-up and post-silicon debug
Requirements summary:
- 20+ years in SoC or system architecture through tape-out and production
- Deep expertise in interconnect fabric and coherency protocols
- Cache hierarchy and memory controller design (DDR5/DDR6, LPDDR5/LPDDR6)
- Working knowledge of PCIe/CXL and System MMU
- Die-to-die interconnect and chiplet partitioning experience
- MS or PhD in EE, CE, CS, or equivalent experience
Tools & skills
Source and dates
Employer career site / ATS feed · lever
- Employer posting date
- 2026-09-22
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-10-26
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Lead |
| Department | Engineering |
| Experience | 20+ years |
| Hours per week | 40 (estimated) |
| Work setting | Office, Laboratory |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Education | Master’s degree (preferred), Professional degree (MD, JD…) (preferred) |
| Fields of study | Electrical Engineering, Computer Engineering, Computer Science |
Summary and details written by AI from the posting; the employer’s posting is the authority.
NUVACORE
Saved company profile
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
NUVACORE is building a new class of CPU for the AI era, designed for maximum performance, efficiency, and scale.
Full company description
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
- LinkedIn followers
- 5,838
- People associated on LinkedIn
- 82
- Reported office locations
- 5201 Great America Pkwy, Suite 215, San Jose, California 95054, US
- 5001 Plaza on the Lk, Suite 320, Austin, TX 78746, US
- 125 Commerce Valley Dr W, Suite 600, Markham, Ontario L3T 7W4, CA
- Other recorded names
- NUVACORE
- Profile identifies a recruitment agency
- No
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
| Field | Value |
|---|---|
| Industry | Technology, Information and Internet |
| Company size | 51-200 employees |
| Headquarters | San Jose, California |
| Organization type | Privately Held |
| Year founded | 2026 |
| Open jobs on Jobsy | 9 |
| View page |
At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. Founded by veteran CPU and system architects from world-class companies and backed by Sequoia Capital, we're a clean-sheet build with no legacy architecture to carry forward.
THE ROLE
We're looking for a Lead SoC Architect to own the SoC architecture surrounding our CPU core — fabric, memory, I/O, power, and security. You'll set architectural direction, make the system-level trade-offs, and work across design, verification, physical design, and software to see them through.
WHAT YOU WILL OWN
Own the overall SoC architecture: processor complex integration, fabric topology, system level cache hierarchy, I/O, power management, and memory subsystem.
Architect the coherent fabric — interconnect/NoC topology, home node design and placement, snoop filtering, and cache coherency protocol (e.g., CHI/ACE-class) — balancing bandwidth, latency, and QoS.
Size, partition, and place system-level caches and determine their interaction with the fabric and home nodes.
Architect the I/O subsystem: PCIe and CXL controller integration and topology.
Drive memory subsystem architecture: DDR5/DDR6 and LPDDR5/LPDDR6 controller design, interleaving, and DRAM QoS/scheduling.
Establish System MMU (SMMU) architecture and I/O virtualization/translation strategy.
Architect die-to-die interconnect and chiplet partitioning for multi-die configurations (e.g., UCIe-class links).
Select, integrate, and evaluate in-house and third-party IP across the SoC, driving customization with vendors or internal IP teams as needed.
Partner with physical design and packaging teams on floorplan, 2.5D/3D packaging, and power/thermal trade-offs.
Provide top down vision/strategy and stay closely aligned with power architecture and management (clocking, reset, power states) and security architecture (domain isolation, secure boot, hardware trust boundaries), even where dedicated teams own execution.
Author and own architecture specs; drive reviews to closure with design, verification, and software.
Review downstream RTL, verification plans, and software/firmware interfaces against the spec.
Support silicon bring-up and post-silicon debug.
Mentor architects and engineers; represent SoC architecture in cross-functional discussions.
WHAT WE'RE LOOKING FOR
20+ years in SoC or system architecture, from definition through tape-out and production.
Deep expertise in coherent/non-coherent interconnect and fabric architecture, home node design, and coherency protocols.
Strong grounding in cache hierarchies and memory controller design (DDR5/DDR6, LPDDR5/LPDDR6).
Working knowledge of PCIe/CXL I/O architecture and System MMU/IO virtualization.
Experience with die-to-die interconnect and chiplet-based partitioning.
Track record integrating in-house and third-party IP, including direct work with vendors and internal IP teams.
Working knowledge of physical design constraints (floorplan, packaging, power delivery, thermal) and their architectural impact.
Working knowledge of power architecture/management and security architecture at the SoC level.
Demonstrated ability to lead architecture definition across a matrixed organization.
Strong written and verbal communication.
MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent experience.
The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.
Journal
Only you can see this. Kept on this device, and in your account when you sign in.