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Physical Design Engineer

@ Chiparama

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Vancouver, British Columbia

Contract5+ years experience
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Overview

Chiparama is hiring a Physical Design Engineer (ASIC) on a 12 to 18 month contract in Vancouver, BC, working onsite with an ASIC Physical Design team. The role owns full-chip physical implementation from RTL to GDSII on advanced technology nodes, including timing signoff, IR/EM analysis and physical verification. The posting requires 5+ years of hands-on ASIC physical design experience and eligibility to work in Canada.

Responsibilities:

  • Own full-chip physical design from RTL to GDSII
  • Drive static timing analysis and timing signoff
  • Perform IR drop, EM and physical verification
  • Optimize designs for power, performance and area
  • Build and improve physical design automation flows

Requirements summary:

  • 5+ years of ASIC physical design experience
  • BS or MS in EE, CE or CS
  • Hands-on experience with Synopsys and Cadence EDA tools
  • Scripting in Tcl, Python or Perl
  • Eligible to work in Canada

Tools & skills

SynopsysCadenceCalibreICV
Source and dates

Source type not verified · apify-linkedin

Employer posting date
2026-11-12
First seen by our source
2026-11-14
Source record updated
2026-11-14

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

Job details

SenioritySenior
DepartmentEngineering
Experience5+ years
Travelair: none · ground: none
Work settingOffice
PositionMostly sitting
Physical demandsphysical low · computer high
LanguagesEnglish
EducationBachelor’s degree (required), Master’s degree (required)
Fields of studyElectrical Engineering, Computer Engineering, Computer Science

Summary and details written by AI from the posting; the employer’s posting is the authority.

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Chiparama

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Job description

🚀 We’re Hiring: Physical Design Engineer (ASIC)

📍 Vancouver, BC, Canada (Onsite)

📄 Contract: 12–18 months

We’re hiring a Physical Design Engineer for a leading global networking and semiconductor company. You’ll join an ASIC Physical Design team and own full-chip physical implementation from RTL to GDSII on advanced technology nodes.

What you’ll do

🔹 Own physical design implementation of multi-hierarchy designs: physical-aware synthesis, DFT, floorplanning, placement, CTS and routing

🔹 Drive Static Timing Analysis (STA) and timing signoff closure

🔹 Perform IR Drop/EM analysis and physical verification (DRC/LVS) through signoff

🔹 Optimize designs for Power, Performance and Area (PPA)

🔹 Work with Front-End/RTL teams to understand the design architecture and resolve implementation issues

🔹 Build and improve automation scripts and physical design flows

What we’re looking for

✅ BS/MS in Electrical Engineering, Computer Engineering or Computer Science

✅ 5+ years of hands-on ASIC physical design and implementation experience

✅ Strong skills in floorplanning, PnR, CTS, timing closure and hierarchical design

✅ Hands-on experience with industry-standard EDA tools (Synopsys, Cadence; Calibre/ICV for PV)

✅ Experience with EM/IR and physical verification signoff

✅ Scripting in Tcl, Python or Perl

✅ Eligible to work in Canada

Nice to have

➕ Formal verification (LEC) experience

➕ Experience with advanced nodes (5nm/3nm) and complex SoC integration

📩 Interested? DM me or comment “Interested” and I’ll reach out. Referrals are welcome!

Equal Employment Opportunity: We are an equal opportunity employer. All qualified applicants will be considered for employment without regard to race, colour, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, Indigenous status, veteran status, or any other characteristic protected by applicable law. We are committed to an inclusive and accessible hiring process. Accommodations are available on request at any stage.

#Hiring #PhysicalDesign #ASIC #VLSI #Semiconductor #RTLtoGDSII #STA #VancouverJobs #CanadaJobs #ContractJobs #HardwareEngineering

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