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Physical Design Engineer

@ Mirafra Technologies

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Canada

Full-time
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Overview

Mirafra Technologies is hiring a full-time Physical Design Engineer focused on static timing analysis, timing closure on sub-nanometer nodes, and automating physical design flows in Tcl and Python with AI-assisted coding tools. The role requires a degree in electrical, computer or microelectronics engineering and strong STA and scripting skills.

Responsibilities:

  • Execute static timing analysis and timing signoff across implementation phases
  • Write and maintain Tcl and Python scripts for EDA tool flows
  • Analyze setup, hold, crosstalk, IR drop and clock path issues
  • Collaborate with RTL and synthesis teams on PPA optimization
  • Build regression tests and document automated methodologies

Requirements summary:

  • Bachelor's or Master's in electrical, computer or microelectronics engineering
  • In-depth STA knowledge with SDC and signoff tools
  • Strong Tcl and Python coding skills
  • Experience with Copilot or LLM-driven coding tools
  • Sound knowledge of digital CMOS and PnR flows

Tools & skills

PrimeTimeTempusICC2Fusion CompilerInnovusGitHub CopilotGit
Source and dates

Source type not verified · apify-linkedin

Employer posting date
2026-11-12
First seen by our source
2026-11-14
Source record updated
2026-11-14

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

Job details

DepartmentEngineering
Hours per week40 (estimated)
Work settingOffice
PositionMostly sitting
Physical demandsphysical low · computer high
EducationBachelor’s degree (required), Master’s degree (required)
Fields of studyElectrical Engineering, Computer Engineering, Microelectronics

Summary and details written by AI from the posting; the employer’s posting is the authority.

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Mirafra Technologies

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FieldValue
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Job description

Role Overview

We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation. In this role, you will be responsible for driving timing closure across complex, sub-nanometer process nodes while leveraging next-generation development tools. You will play a key role in developing, optimizing, and automating physical design workflows using Tcl and Python, incorporating AI-assisted development tools like GitHub Copilot to accelerate script delivery and engineering efficiency.

Key Responsibilities

  • Static Timing Analysis (STA): Execute timing signoff, constraint validation, multi-corner multi-mode (MCMM) analysis, and timing closure across all phases of physical implementation.
  • Flow Automation & Scripting: Write, maintain, and enhance robust automated scripts using Tcl and Python to streamline EDA tool flows (place & route, synthesis, signoff).
  • AI-Assisted Development: Utilize Copilot-assisted development tools to rapidly build, refactor, and test flow automation scripts, optimizing operational productivity.
  • Timing & Power Optimization: Analyze setup/hold violations, crosstalk, IR drop, and clock path issues, collaborating closely with RTL and synthesis teams to achieve optimal PPA (Power, Performance, Area).
  • Process Improvement: Standardize scripting frameworks, build continuous regression tests for physical design tools, and document automated methodologies for the broader team.

Qualifications

Required Skills & Experience:

  • Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
  • Core STA Expertise: In-depth understanding of Static Timing Analysis principles, timing constraints (SDC), clock jitter, skew, cross-talk noise, and signoff methodologies using industry tools (e.g., Synopsys PrimeTime or Cadence Tempus).
  • Scripting Proficiency: Strong hands-on coding ability in Tcl (for EDA tool integration) and Python (for data processing and workflow automation).
  • Modern Development Tooling: Direct experience or strong familiarity with Copilot-assisted coding/script development tools (or LLM-driven coding tools) to write, debug, and optimize scripts efficiently.
  • VLSI Fundamentals: Sound understanding of digital CMOS logic, place and route (PnR) flow fundamentals, and physical verification concepts.

Preferred Qualifications:

  • Experience with automated tool API integrations (e.g., Synopsys ICC2/Fusion Compiler, Cadence Innovus APIs).
  • Experience implementing CI/CD pipelines or automated regression frameworks for hardware design flows.
  • Background in Git or modern version control systems for managing Tcl/Python script repositories.

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