Positron delivers vendor freedom and faster inference for both enterprises and research teams, by allowing them to use hardware and software explicitly designed from the ground up for generative and large language models (LLMs). Through lower power usage and drastically lower total cost of ownership (TCO), Positron enables you to run popular open source LLMs to serve multiple users at high token rates and long context lengths. Positron is also designing its own ASIC to…
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
Building next generation hardware+software appliances for machine learning applications
Positron delivers vendor freedom and faster inference for both enterprises and research teams, by allowing them to use hardware and software explicitly designed from the ground up for generative and large language models (LLMs). Through lower power usage and drastically lower total cost of ownership (TCO), Positron enables you to run popular open source LLMs to serve multiple users at high token rates and long context lengths. Positron is also designing its own ASIC to expand from inference and fine tuning to also support training and other parallel compute workloads.
Currency and observation date were not supplied; this is not a current valuation or a funding round.
Positron AI has 8 open jobs in Canada as of November 6, 2026.
No matching filters. Try another name.
Positron AI
8+ YOECandidates need 8+ years in ASIC emulation or verification, including large Palladium installations, and a BS or MS in electrical engineering, computer engineering or computer science. Strong skills in SystemVerilog, Verilog, C/C++, Python, Tcl and Bash are required, along with knowledge of PCIe, DDR and AXI protocols.
Cadence Palladium, Verdi, SimVision
Positron AI
5+ YOECandidates need a Bachelor's degree or equivalent practical experience and 5+ years of FPGA or ASIC design, including shipped products. They need hands-on SystemVerilog and experience with high-end Intel and Xilinx (AMD) FPGAs.
SystemVerilog, Intel FPGA, Xilinx (AMD) FPGA, cocotb
Positron AI
5+ YOECandidates need 5 to 8 years of physical design experience and at least one advanced-node tapeout. Strong Innovus or ICC2 skills and knowledge of timing, power and clock tree synthesis are required.
Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk
Positron AI
8+ YOECandidates need 8+ years of ASIC design experience with a strong power focus, hands-on low-power design and UPF/CPF experience, and proficiency with PrimePower, Joules and Tcl or Python. Advanced process node experience and a track record of meeting power targets on production silicon are required.
PrimePower, Joules, Tcl, Python, UPF, CPF
Positron AI
8+ YOEPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.
Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl
Positron AI
8+ YOECandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.
SystemVerilog, Python, Tcl, Make, UVM, cocotb
Positron AI
15+ YOECandidates need 15+ years of ASIC architecture experience, deep expertise in AI accelerators and high-performance SoCs, and hands-on work with memory and interconnect performance models. Strong hardware/software co-design and excellent communication skills are required.
Machine learning, ML, Communication skills, Firmware, Research
Positron AI
8+ YOECandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.
Cadence Genus, Synopsys Design Compiler, Tcl, Python
1 companies