Log in Sign up free
Apply now

Posted 2 days ago

RTL Design Engineer – PCIe

@ Yochana

View all jobs

Canada

Contract
Apply now
SIGNALS

Overview

Yochana is hiring a contract RTL Design Engineer focused on PCIe to write and implement digital logic in Verilog and SystemVerilog. The work covers micro-architecture development, RTL implementation, and verification of PCIe Gen3/Gen4/Gen5 protocols.

Responsibilities:

  • RTL design in Verilog/SystemVerilog
  • PCIe Gen3/Gen4/Gen5 protocol verification
  • Micro-architecture development and RTL implementation
  • Debugging and problem-solving

Requirements summary:

  • Hands-on RTL design in Verilog/SystemVerilog
  • Digital design fundamentals (FSM, CDC, reset, low-power)
  • Knowledge of synthesis constraints and timing
  • Familiarity with Lint, CDC, STA and low-power verification
  • Bachelor's or Master's in ECE, EEE or related field preferred

Tools & skills

VerilogSystemVerilog
Source and dates

Source type not verified · apify-linkedin

Employer posting date
2026-11-10
First seen by our source
2026-11-11
Source record updated
2026-11-11

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

Job details

DepartmentEngineering
Work settingOffice
PositionMostly sitting
Physical demandsphysical low · computer high
EducationBachelor’s degree (preferred), Master’s degree (preferred)
Fields of studyElectrical and Computer Engineering, Electrical and Electronics Engineering, Electronics Engineering

Summary and details written by AI from the posting; the employer’s posting is the authority.

Apply now
FieldValue
Open jobs on Jobsy14
Job description

Key Responsibilities & Required Skills
Strong hands-on experience in RTL Design using Verilog/SystemVerilog.
Hands-on experience in verification of PCIe Gen3/Gen4/Gen5 protocols.
Good understanding of digital design fundamentals, including FSM design, pipelining, CDC, reset architecture, synchronizers and low-power design concepts.
Experience in micro-architecture development and RTL implementation.
Knowledge of synthesis constraints and timing concepts.
Familiarity with Lint, CDC, STA and low-power verification methodologies.
Strong debugging and problem-solving skills.
Preferred Qualifications
Bachelor's or Master's degree in ECE, EEE, Electronics or a related engineering discipline.
Relevant experience in RTL Design and/or PCIe Design Verification.
Good understanding of ASIC design and verification flows.

Similar jobs

  • RTL Design Engineer

    Canada
    Full Time

    HCLTech

    Candidates need hands-on RTL design experience in Verilog or SystemVerilog and PCIe protocol knowledge, preferably Gen3 to Gen5. They should understand digital design fundamentals such as FSMs, pipelining, CDC, reset architecture and low-power design, plus synthesis, timing, lint, CDC and STA methods.

    Verilog, SystemVerilog

  • RTL Design Engineer

    Markham, ON
    Full Time

    Advanced Micro Devices, Inc

    Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong Verilog and SystemVerilog skills, scripting experience, and knowledge of AXI, AHB and AMBA protocols. Experience with ASIC design flows and processor or security subsystems is preferred.

    Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

    RTL Design Engineer

    Markham, ON
    Full Time

    Advanced Micro Devices, Inc

    Candidates need a bachelor's or master's degree in electrical or computer engineering or a related field, with strong Verilog and SystemVerilog skills and knowledge of CPU and embedded processor architectures. Experience with AXI, AHB, AMBA and ASIC design tools is preferred.

    Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

    RTL Design Engineer

    Markham, ON
    Full Time

    Advanced Micro Devices, Inc

    Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. Strong analytical, communication and teamwork skills are expected, along with scripting in Python or Perl.

    RTL, DFT, Firmware, Analytical skills, Problem solving, Attention to detail

  • RTL Design Engineer

    Markham, ON
    Full Time

    AMD, Inc.

    AMD needs candidates with a Bachelor's or Master's degree in an electrical, computer or related engineering field, with Master's preferred. Strong skills in Verilog, SystemVerilog and scripting such as Python, Tcl or Perl are expected, along with knowledge of processor subsystems and ASIC design flows.

    Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

    RTL Design Engineer

    Markham, ON
    Full Time

    AMD, Inc.

    Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.

    Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools

    RTL Design Engineer

    Markham, ON
    Full Time

    AMD, Inc.

    Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. A bachelor's or master's degree in electrical engineering or equivalent is preferred.

    Python, Perl

  • RTL Design Engineer - AI Tools

    Toronto, ON
    $100–$175/hr

    Mercor

    3+ YOECandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog, SystemVerilog and UVM skills, and solid digital design fundamentals. Experience with ASIC design flows and EDA tools is also required.

    Verilog, SystemVerilog, UVM, EDA tools

Locations & environments

Locations

All of CanadaRemote · Hybrid · On-site · Field

Pro tip: add remote jobs to widen your search.

Exclude locations

Workplace type

Company jobs in these results

These are this company’s jobs loaded in your current search. The company may have more openings.