Posted 50 months ago
Senior ASIC Design Verification Engineer
@ Talentlab
Toronto, Ontario
Overview
Talentlab is recruiting a Senior ASIC Design Verification Engineer for a fast-growing, recently public semiconductor company that makes connectivity solutions for data-centric systems. The role centres on UVM and C/C++ verification of complex SoC silicon for server, storage and networking.
Responsibilities:
- Develop UVM-based verification environments and test-plans
- Write C/C++ and System Verilog tests and sequences
- Debug RTL failures with designers
- Automate verification infrastructure with Perl or Python
- Integrate third-party verification IP for communication protocols
Requirements summary:
- Bachelor's in electrical engineering (Master's preferred)
- 2+ years supporting complex SoC silicon products
- Hands-on UVM and C/C++ verification experience
- Experience with DPI/PLI integration of C/C++ in System Verilog
- Experience with protocol VIPs such as PCIe Gen-3+, Ethernet, DDR, NVMe
Tools & skills
Source and dates
Source type not verified · cats
- Employer posting date
- 2022-09-14
- First seen by our source
- 2026-10-15
- Source record updated
- 2026-11-05
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Software development |
| Experience | 2+ years |
| Work setting | Office, Laboratory |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Bachelor’s degree (required), Master’s degree (preferred) |
| Fields of study | Electrical engineering |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Talentlab
| Field | Value |
|---|---|
| Open jobs on Jobsy | 26 |
Job Description:
We have partnered with a fast growing semiconductor company that recently went public. Our client is a leader in purpose-built connectivity solutions for data-centric systems. Currently they are looking for experienced ASIC Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.
Basic Qualifications:
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
required, and a Maser’s is preferred. - 2+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or
Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
customer meetings in advance, and to work with minimal guidance and supervision. - Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!.
Required Experience:
- Experience with integrating C/C++ in System Verilog environments using DPI/PLI
- Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
- Experience in developing infrastructure and tests in a hybrid directed and constrained random
environments - Must be able to work independently to develop test-plans, and related test-sequences in UVM to
generate stimuli and work collaboratively with RTL designers to debug failures. - Develop user-controlled random constraints in transaction-based verification methodology. Experience
writing assertions, cover properties and analyzing coverage data - Must have prior experience using Verification IPs from 3rd party vendors for communication protocols
such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc. - Develop VIP abstraction layers to simplify and scale verification deployments
Preferred Experience:
- S/W debugging for SoC based designs in the area of kernel/device-drivers/u-boot
- Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol.
- Experience in memory technologies like DDR4/DDR5/HBM.
- Experience with FPGA-based verification/emulation.
All qualified and interested applicants can apply directly to Aaron Ravensbergen by sending an email with attached resume to [email protected]. You may also apply directly on our website at www.talentlab.com. Although we thank all applicants for their interest, only those in consideration will be contacted.
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