Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
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Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services.
We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
5+ YOECandidates need a PhD with 5+ years or a Master's with 8+ years of hands-on analog IC design experience. Strong CMOS skills, detailed SerDes sub-circuit design experience and SPICE simulation expertise are required.
Candidates need a bachelor's degree in a related field, hands-on experience across Linux and Windows, and scripting ability in Bash, PowerShell or Python. Strong methodical troubleshooting and clear English communication are required.
6+ YOECandidates need a BSEE or MSEE and 6+ years of digital design and verification experience. They must have SystemVerilog and UVM testcase experience, strong debugging skills, and scripting ability in Python or Perl.
10+ YOECandidates need a Bachelor's, Master's or PhD in computer or electrical engineering, or equivalent experience, with 10+ years in a related field. They need strong skills in digital logic and firmware development, proficiency in C, Verilog and SystemVerilog/UVM, and experience leading complex projects.
8+ YOECandidates need a bachelor's degree in a related field or equivalent experience, typically 8+ years building production enterprise web applications, and deep PANN stack experience. They also need strong database, cloud, container and CI/CD skills, practical AI experience, and strong communication abilities.
8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.
Candidates need proven experience with high-speed interface signaling, signal and power integrity analysis, and EDA tools such as HFSS, Ansys, HSPICE, Raptor and ADS. They also need strong communication skills and board-level and on-chip IO design knowledge.
6+ YOECandidates need a PhD with 6+ years or a Master's with 8+ years of analog and mixed-signal IC design experience, including FinFET circuit design. Strong transistor-level CMOS and SPICE simulation skills are required.
7+ YOECandidates need 7-8+ years of experience with a bachelor's degree, 5-6+ with a master's, or 3-4+ with a PhD, in an engineering or computer science field. They need strong skills in CAD or simulation infrastructure, scripting in Python, Tcl or Shell, and Linux environments.
10+ YOECandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.
7+ YOECandidates need a bachelor's degree in electrical and electronics engineering with 7+ years of applications, verification or emulation experience, or a master's with 5+ years. They need hands-on emulation platform experience, HDL and UVM skills, and scripting in Python, Perl or TCL.
6+ YOECandidates need a Bachelor's or Master's in electrical or electronics engineering (or equivalent experience), 6-8+ years of high-speed hardware validation, and expert Cadence Allegro skills. They also need strong signal integrity knowledge and experience with oscilloscopes, logic analyzers and network analyzers.
9+ YOECandidates need 9+ years of ASIC physical design experience on complex SoC or test chip projects at advanced nodes. They must know the full physical design flow and tools such as Design Compiler, PrimeTime, IC Compiler II, Calibre and RedHawk, and must be authorized to work in the USA.
Design Compiler, PrimeTime, IC Compiler II, ICV, Calibre, RedHawk
Candidates need a PhD, or a Master's with equivalent hands-on experience, in photonics, optics or a related field. They also need strong C++ and Python skills and experience with numerical methods such as FDTD, DGTD or RCWA.
8+ YOECandidates need a master's degree with 8+ years or a PhD with 6+ years of analog circuit design experience. Experience with op-amps, current mirrors and bandgaps is required, and SERDES or DDR knowledge is strongly desired.
10+ YOECandidates need a master's degree or equivalent experience and 10+ years of digital ASIC design, ideally in high-speed or mixed-signal work. They need strong Verilog or VHDL skills, clock domain crossing knowledge, synthesis and DFT experience, and experience working with verification teams.
4+ YOECandidates need an MS in Mechanical Engineering or related field with 6+ years in engineering software, a BS with 8+ years, or a PhD with 3+ years. They must have 4+ years of customer-facing application engineering and strong CFD and thermal skills, plus hands-on Ansys experience.
Candidates need advanced Python skills for full stack work, cloud and container experience, working knowledge of generative AI and LLM applications, and strong distributed systems and API design. Leadership and mentoring ability is also required.
8+ YOECandidates need 8+ years of CMOS analog or mixed-signal design experience and strong expertise in transistor-level and SerDes circuits. Hands-on FinFET layout, SPICE and scripting skills, and knowledge of reliability and ESD design are also required.
2+ YOECandidates need a bachelor's degree in a technical field and 2+ years of software development. They need strong C++, data structures and geometric algorithm skills, with meshing experience a strong plus.
5+ YOECandidates need a bachelor's or master's degree in computer science or a related field, plus 5+ years of production software experience. Strong skills in C#, .NET, Python and Angular, and the ability to design software frameworks, are required.
10+ YOECandidates need a Bachelor's or Master's in Electrical or Computer Engineering and 10+ years of ASIC digital implementation experience. Deep expertise with Fusion Compiler or ICC2, high-speed IP experience, and Tcl and Python scripting are required.
5+ YOECandidates need a bachelor's degree in a technical field and 5+ years of software development (3+ with a master's or PhD). Strong C++ skills, performance optimization and GPU experience such as CUDA or OpenCL are needed.
12+ YOECandidates need at least 12 years of related experience in high-speed interfaces and mixed-signal design. They also need skills in custom analog design, simulation, verification, debugging, and writing technical specifications.
Documentation, Communication skills, Troubleshooting, Debugging