Analog Design, Manager - 18463
Kanata, ONS
Synopsys
8+ YOE2+ MgmtCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.
SPICE, Verilog-A, Industry-standard simulation tools