Posted 2 months ago
ASIC Digital Design, Principal Engineer-18731
@ Synopsys
Mississauga, Ontario
Overview
Synopsys is hiring a Principal ASIC Digital Design engineer to lead verification strategy for next-generation PCIe PHY IP. The role involves defining verification plans, building testbenches, verifying LTSSM, PIPE and equalization behaviour, and mentoring engineers. The posting gives a base salary range of $146,000 to $219,000 and states the role is not remote.
Responsibilities:
- Define and drive verification strategy for PCIe PHY IPs
- Build and execute block- and subsystem-level testbenches
- Verify LTSSM, PIPE, power management and equalization
- Debug failures and drive root-cause resolution
- Mentor engineers and promote verification best practices
Requirements summary:
- Extensive mixed-signal ASIC/IP verification experience
- Strong PCIe and PCIe PHY verification expertise
- SystemVerilog, UVM and assertions experience
- Experience closing coverage on complex IP
- Proven ability to mentor and lead technical work
Tools & skills
Source and dates
Source type not verified · talentbrew
- Employer posting date
- 2026-09-20
- First seen by our source
- 2026-10-11
- Source record updated
- 2026-10-11
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Lead |
| Department | Engineering |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Encouraged to apply | People with disabilities |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Synopsys
Saved company profile
Historical company information from a saved The Jobs API profile (LinkedIn/Crunchbase fields). It is not live-verified; figures may have changed. Missing values remain unknown.
Our Technology. Your Innovation.
Full company description
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
- LinkedIn followers
- 863,172
- People associated on LinkedIn
- 28,193
- Reported office locations
- 675 Almanor Ave, Sunnyvale, California 94085, US
- Other recorded names
- Synopsys
- Synopsys Inc
- Specialties
- EDA
- Computer Software
- Semiconductor IP
- Software Quality
- and Software Security
- Profile identifies a recruitment agency
- No
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of…
| Field | Value |
|---|---|
| Industry | Software Development |
| Company size | 10,001+ employees |
| Headquarters | Sunnyvale, California |
| Organization type | Public Company |
| Specialties | EDAComputer SoftwareSemiconductor IPSoftware Qualityand Software Security |
| Open jobs on Jobsy | 49 |
| View page |
Category Engineering Hire Type Employee Job ID 18731 Base Salary Range $146000-$219000 Remote Eligible No Date Posted 09/20/2026
We Are
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to intelligent systems. We are a leader in chip design, verification, and IP integration, enabling customers to accelerate innovation and bring high-performance silicon and software solutions to market faster.
Our team develops high-speed silicon IP solutions with a primary focus on PCIe PHY technology. These IPs enable customers to integrate advanced connectivity into SoCs faster while meeting demanding performance, power, area, and reliability targets. We are looking for a senior verification leader to drive the strategy, execution, and quality of next-generation PCIe PHY IP verification.
You Are
You are an experienced ASIC Verification Engineer with a strong track record of delivering high-quality mixed-signal IP products, especially high-speed SerDes-based PHYs. You bring deep expertise in digital verification methodologies and have strong domain knowledge in PCIe PHY architectures, link behavior, LTSSM, power management, equalization, and interoperability requirements.
You are comfortable defining and driving verification strategy for complex PHY IPs, building scalable verification environments, and collaborating closely with design, analog, systems, and architecture teams. You are a proactive problem solver who can work with minimal supervision, communicate clearly across technical disciplines, and lead verification efforts that improve product quality and execution efficiency.
What You’ll Be Doing
- Define and drive the verification strategy and functional quality for next-generation PCIe PHY IPs.
- Develop comprehensive verification plans for complex mixed-signal digital designs with primary emphasis on PCIe PHY functionality and protocol compliance.
- Architect, develop, and execute advanced testbench environments for block-level and subsystem-level verification.
- Verify key PCIe PHY features such as LTSSM behavior, PIPE interface interactions, link initialization and training, power management, equalization flows, error handling, and compliance-related scenarios.
- Work closely with design, analog, firmware, architecture, and validation teams to ensure robust coverage of cross-functional use cases.
- Use advanced verification methodologies, including constrained-random, assertion-based verification, coverage-driven verification, and debug automation, to achieve high-quality results.
- Analyze failures, root-cause complex issues, and drive resolution across design and verification domains.
- Mentor and guide other engineers, promote verification best practices, and help build a culture of technical excellence and continuous improvement.
- Communicate effectively with internal stakeholders and customers to align on technical goals, verification quality, and deliverables.
What You’ll Need
- Extensive experience in mixed-signal ASIC/IP verification.
- Strong expertise in PCIe and PCIe PHY verification.
- Solid understanding of high-speed SerDes/PHY architecture and digital control verification in mixed-signal environments.
- Hands-on experience with modern verification methodologies such as SystemVerilog, UVM, assertions, and coverage-driven verification.
- Experience developing verification plans, building reusable verification environments, and closing coverage for complex IP products.
- Strong debugging and problem-solving skills, with the ability to work independently and drive issues to closure.
- Excellent communication and collaboration skills for working across global, cross-functional teams.
- Proven ability to mentor engineers and lead technical verification activities.
Who You Are
- A technical leader who can drive verification excellence for complex PCIe PHY IP products.
- A mentor who develops talent, shares knowledge, and raises the bar for the team.
- A proactive problem solver who thrives in technically challenging environments.
- A strong communicator who can clearly convey complex concepts to both technical and cross-functional audiences.
- A collaborative team player who values innovation, quality, and execution. #L1-NK4
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].
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