Posted 17 months ago
Staff ASIC Design Engineer – AI/ML Hardware IP
@ Talentlab
Toronto, Ontario
Overview
Talentlab is hiring a Staff ASIC Design Engineer for a leading global semiconductor company to architect and develop next-generation AI/ML hardware IP. The role covers micro-architecture, RTL design, and integration of sub-IP blocks into SoC components, and is on-site in Canada.
Responsibilities:
- Define micro-architecture and detailed specifications from high-level requirements
- Develop performance-optimized RTL in Verilog/SystemVerilog
- Integrate sub-IP blocks into SoC components and subsystems
- Conduct Lint, CDC, and synthesis flow analysis
- Collaborate with verification teams on test plans and regression debugging
Requirements summary:
- 5+ years of hands-on ASIC design experience
- Proficiency in Verilog/SystemVerilog, RTL design, and logic synthesis
- Experience with clock/reset architecture, bus protocols, and power-aware design
- Experience with CDC, lint, synthesis, timing, and simulation tools
- Bachelor's with 5+ years, Master's with 3+ years, or PhD with 2+ years in electrical or computer engineering
- Legally authorized to work on-site in Canada
Tools & skills
Source and dates
Source type not verified · cats
- Employer posting date
- 2025-06-02
- First seen by our source
- 2026-10-15
- Source record updated
- 2026-11-05
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Seniority | Senior |
| Department | Engineering |
| Experience | 5+ years |
| Travel | air: none · ground: none |
| Work setting | Office |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Bachelor’s degree (required), Master’s degree (preferred), Doctorate (preferred) |
| Fields of study | Electrical Engineering, Computer Engineering |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Talentlab
| Field | Value |
|---|---|
| Open jobs on Jobsy | 26 |
Position: Staff ASIC Design Engineer – AI/ML Hardware IP
Location: On-site in Canada
We're partnering with a leading global semiconductor company to find a Staff ASIC Design Engineer to help architect and develop next-gen AI/ML hardware IP. This role is ideal for someone who thrives in RTL design, micro-architecture development, and hardware integration , particularly in areas like clock domain crossing, power optimization, and formal verification.
Key Responsibilities:
Define micro-architecture and detailed specifications from high-level design requirements.
Develop performance-optimized RTL design (Verilog/SystemVerilog) with strong area and power efficiency.
Integrate sub-IP blocks into larger SoC components and subsystems.
Conduct Lint, CDC, and synthesis flow analysis.
Collaborate with verification teams to define test plans, debug regressions, and analyze coverage reports.
Create SVA assertions for white-box and formal verification.
Communicate effectively across cross-functional teams to ensure timely execution of deliverables.
What They’re Looking For:
5+ years of hands-on ASIC design experience (verification, RTL, integration, etc.).
Proficiency in Verilog/SystemVerilog, RTL design, and logic synthesis.
Experience with one or more of the following:
Clock/reset architecture, FIFOs, bus protocols (AHB/AXI), memory control
AI/ML hardware blocks
Power-aware design using UPF, CLP, PowerPro, etc.
CDC and lint tools (Spyglass, 0-in, SVA)
Synthesis and timing tools (Design Compiler, PrimeTime, Formality)
Simulation tools (VCS, Verdi, Questa, Xcelium)
Scripting in Python, Perl, TCL, or C
Required Education/Experience:
Bachelor’s (with 5+ years), Master’s (3+ years), or PhD (2+ years) in Electrical Engineering, Computer Engineering, or related field.
Legally authorized to work on-site in Canada.
Journal
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