Sr/Staff Digital Design Engineer
Toronto, ONLightmatter
5+ YOELightmatter needs candidates with a bachelor's degree in electrical or computer engineering and at least 5 years of ASIC or high-speed chip design experience, including multiple successful tape-outs. Candidates must know SystemVerilog or Verilog and have proven experience debugging logic and mixed-signal simulations.
SystemVerilog, Verilog, Synopsys VCS, Cadence Xcelium, Questa
Staff/Sr. Staff Design Verification Engineer
Toronto, ONLightmatter
8+ YOECandidates need a bachelor's degree in an engineering field and at least 8 years of design verification and SystemVerilog experience. Python experience of 2 or more years, expertise with the UVM library and experience with Xcelium, ModelSim, Questa or VCS are also required.
Xcelium, ModelSim, Questa, VCS, UVM, SystemVerilog