Posted 5 days ago
Mixed Signal Design Engineer
@ Ciena Canada ULC
Ottawa, Ontario
Overview
Ciena Canada ULC is hiring a full-time Mixed Signal Design Engineer on its Wavelogic team, which develops high-speed analog circuits for fiber-optic modems. The role designs high-precision Sigma-Delta DAC and ADC circuits and writes SystemVerilog and IBIS-AMS models for SerDes IP at 56 to 448 Gbd. The posted annual salary is $93,100 to $148,700 CAD.
Pay:
$93,100–$148,700 a year
Responsibilities:
- Design high-precision Sigma-Delta DAC and ADC for control and monitoring
- Design SystemVerilog models for analog macros
- Design IBIS-AMS models for high-speed SerDes IP at 56 to 448 Gbd
- Create design specification documents
- Support system, analog, digital, DSP and lab bring-up teams
Requirements summary:
- Engineering, computer science or applicable science degree (BEng/BSc to PhD)
- Design experience in latest CMOS and BiCMOS technology
- Proficiency with Cadence, Synopsys and Siemens EDA tools
- Familiarity with SystemVerilog, Verilog-AMS, Matlab/Simulink, C/C++, Python
- Ability to work independently and collaboratively
- Strong English writing and presentation skills
Tools & skills
Benefits mentioned
Source and dates
Employer career site / ATS feed · workday
- Employer posting date
- 2026-11-01
- First seen by our source
- 2026-10-08
- Source record updated
- 2026-11-03
These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.
Job details
| Department | Engineering |
| Hours per week | 40 (estimated) |
| Work setting | Office, Laboratory |
| Position | Mostly sitting |
| Physical demands | physical low · computer high |
| Languages | English |
| Education | Bachelor’s degree (required), Master’s degree (preferred), Doctorate (preferred) |
| Fields of study | Electrical engineering, Computer engineering, Computer science, Applied science |
| Perks mentioned | Generous paid time off, Retirement plan, Performance bonus, Stock or equity, Wellness |
Summary and details written by AI from the posting; the employer’s posting is the authority.
Ciena Canada ULC
| Field | Value |
|---|---|
| Open jobs on Jobsy | 75 |
As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.
How You Will Contribute:
The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track record of success over 30 years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions. Reporting to the Senior Manager of Analog Engineering, your role will be:
- Designing the high precision Sigma-Delta DAC and ADC for control and monitoring
- Designing the SystemVerilog models for various analog macros
- Designing the IBIS-AMS models for the high-speed DAC and ADC based SerDes IP running at 56Gbd, 112Gbd, 224Gbd, and 448Gbd
- Creating Design Specification Document
- Interacting with and providing support to the system team, analog team, the digital team, the DSP team, the signal integrity team, the hardware team, firmware team, and the analog lab bring-up team.
The Must Haves:
- Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc, MEng/MSc, or PhD level
- Design experience in the latest CMOS and BiCMOS technology
- Proficiency with Cadence Virtuoso/Xcelium/AMS, Synopsys VCS/StarRC, Siemens Questa/Formal/Calibre/SymphonyAMS/AFS
- Familiarity with SystemVerilog, VerilogAMS, VerilogA, Matlab/Simulink, C/C++, Python languages
- Ability to work independently and collaboratively with team members
- Skills of writing and presenting in English
Assets:
- Knowledge of UVM, Git, Gradle, Google Tests
- Experience with the RF and Signal Integrity tools
- DSP, digital, and analog design and modelling in high SerDes application
- AI tools for automation
Pay Range: The annual salary range for this position is $93,100 - $148,700 CAD.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
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