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Posted 19 months ago

Senior Design Verification Engineer

@ Talentlab

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Toronto, Ontario

3+ years experience
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SIGNALS

Overview

Talentlab is hiring a Senior Design Verification Engineer for a client in semiconductors that accelerates high-performance data communication. The role covers verification planning, testbench and simulation work, debugging design bugs, and post-silicon validation for SerDes, PHY, DSP and mixed-signal designs. Candidates should have 3 to 8 years of design verification experience, with SystemVerilog and UVM as core skills.

Responsibilities:

  • Review design specifications and build verification plans
  • Build testbenches, run simulations and debug design bugs
  • Lead and coordinate verification tasks with team members
  • Integrate third-party VIPs for protocol compliance testing
  • Support post-silicon validation and bring-up

Requirements summary:

  • 3 to 8 years of design verification experience
  • Strong SystemVerilog and UVM skills
  • Experience verifying SerDes PHYs, DSPs and mixed-signal designs
  • Knowledge of Ethernet and PCIe protocols is highly desirable
  • Familiarity with formal and UPF power-aware verification

Tools & skills

SystemVerilogUVMPythonPerlC/C++GNU MakeMATLAB
Source and dates

Source type not verified · cats

Employer posting date
2025-04-08
First seen by our source
2026-10-15
Source record updated
2026-11-05

These dates describe the source record, not a live verification that the employer is still hiring. Check the original posting.

Job details

SenioritySenior
DepartmentSoftware development
Experience3+ years
Work settingOffice, Laboratory
PositionMostly sitting
Physical demandsphysical low · computer high
LanguagesEnglish

Summary and details written by AI from the posting; the employer’s posting is the authority.

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Talentlab

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FieldValue
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Job description

Senior Design Verification Engineer

Our client is a key player in advancing digital technology by accelerating high-performance data communication—from AI and the metaverse to seamless video and beyond. Their technology is foundational to innovation across data-heavy industries such as data centers, AI, networking, storage, 5G, and autonomous vehicles. Known for their cutting-edge solutions and reliable execution, they help shape the future of digital systems.

The Digital Design Verification team fosters a collaborative, growth-oriented culture where engineers are encouraged to take on new challenges, learn continuously, and contribute to impactful projects. This group is dynamic, supportive, and a great fit for professionals looking to build their career in semiconductors.

What You’ll Do

  • Review design specifications and develop robust verification plans.

  • Build testbenches, run simulations, and debug failures to uncover design bugs.

  • Take initiative in leading, planning, and coordinating verification tasks with team members.

  • Create behavioral models of analog circuits.

  • Support bit-matching between RTL designs and MATLAB system models.

  • Integrate third-party VIPs for compliance testing of standard protocols.

  • Prepare design IP releases for customer delivery.

  • Collaborate in post-silicon validation and bring-up efforts.

  • Work closely with cross-functional teams—including Design, Systems, Analog, Firmware, and PD—to ensure final verification closure.

  • Continuously improve verification methodologies, tools, and team processes.

What You’ll Need

  • 3 to 8 years of relevant experience in design verification.

  • Strong skills in SystemVerilog and UVM for constrained-random verification.

  • Experience verifying SerDes PHYs, DSPs, and mixed-signal analog designs.

  • Knowledge of Ethernet and PCIe protocols is highly desirable.

  • Familiarity with formal verification and power-aware UPF verification techniques.

  • Proficiency in SystemVerilog, UVM, Python, Perl, C/C++, and GNU Make.

Please reach out to [email protected] with your resume if you're a fit for the position and interested in learning more.

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