Design Verification Engineer

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• 1d

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• 25d

  Design Verification Engineer - Fully Remote | Upto $175/hr

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• 28d

  Senior Design Verification Engineer

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  3+ YOETalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

• 28d

  Design Verification Engineer

  Markham, ON

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  AI

  AMD, Inc.

  AMD asks for advanced ASIC functional verification experience and hands-on work on multiple projects or tapeouts. Candidates need Verilog, SystemVerilog, UVM, scripting skills, and a Bachelor's or Master's in Computer or Electrical Engineering.

  Verilog, UVM, Makefiles, Perl, Python, Ruby

• 1mo

  Design Verification Engineer, Annapurna Labs

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  Amazon Development Centre Canada ULC

  4+ YOECandidates need a bachelor's degree in electrical engineering or a related field and at least 4 years of design verification experience using constrained-random simulation such as UVM. Strong debugging skills across IP, SoC and full-system levels are required.

  UVM, Python, Perl, C++

  1mo

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  Amazon Development Centre Canada ULC

  8+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.

  UVM, formal verification tools, emulation platforms, Python, Perl

• 1mo

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  Advanced Micro Devices, Inc

  Candidates need hands-on hardware verification experience across multiple projects or tapeouts, with SystemVerilog, UVM, Verilog and scripting skills. A Bachelor's or Master's in Computer or Electrical Engineering is expected.

  UVM, Verilog, Makefiles, Perl, Python, Ruby

• 1mo

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  Qualcomm Canada ULC

  3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.

  Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers