System Engineer, Application Engineering Principal
Ottawa, ON +1Qualcomm Canada ULC
12+ YOECandidates need a master's or PhD in an engineering or science field and 6 to 12+ years of experience in high-speed communications, DSP or SerDes. Deep knowledge of PAM4 signaling, IEEE 802.3 standards and MATLAB or Python is required.
MATLAB, Python
Cross-Functional Engineer, Staff
Toronto, ON +1Qualcomm Canada ULC
4+ YOECandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ YOECandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
Verification Engineer (Engineer–Senior Level)
Toronto, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in science or engineering with 2+ years of ASIC design or verification experience, or a master's with 1+ year, or a PhD. Strong SystemVerilog and UVM skills, constrained random verification experience and clear communication are required.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
DFT Engineer, Senior
Toronto, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in an engineering or computer science field with 2+ years of hardware engineering experience, or a master's with 1+ year. They need hands-on DFT, ATPG, and test-pattern experience plus scripting skills.
Python, Tcl, Perl
FY27 Intern - Firmware/Embedded Software Engineering Internship - Canada (12 or 16 months)
Toronto, ONQualcomm Canada ULC
1+ YOECandidates need to be enrolled in a bachelor's degree in electrical or computer engineering, engineering science or computer science, with at least one year of academic programming experience in C, C++ or Python. Strong debugging, problem-solving and teamwork skills are needed, and availability must match the 12- or 16-month internship dates.
Git, Linux, FPGA, Verilog, SystemVerilog, GitHub Actions
Connectivity Systems Engineer, Staff
Toronto, ONQualcomm Canada ULC
5+ YOECandidates need a Master's or PhD with 5 years of relevant experience, plus strong mathematical skills in modelling communication systems at 100+ Gbps. Hands-on programming in MATLAB or Python, and experience turning interconnect and amplifier measurements into system models, are required.
MATLAB, Python
Sr ASIC Design Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
2+ YOEQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl
FY27 Intern - Machine Learning Compiler & Performance Engineering Intern - Canada (16 months)
Markham, ONQualcomm Canada ULC
Candidates need proficiency in Python or C++, strong analytical and debugging skills, and good written and verbal communication. They must be pursuing a bachelor's degree in an engineering or computer science field, available May/June 2027 to August/September 2028, and expected to graduate November 2028 or later.
Git, Linux, SSH, CI/CD systems, PyTorch, ONNX
Staff Verification Engineer, Compute Subsystems
Markham, ONQualcomm Canada ULC
5+ YOECandidates need a bachelor's, master's, or PhD in engineering or science with several years of ASIC design or verification experience, plus strong UVM and SystemVerilog skills, bus protocol knowledge, and scripting in Perl or Python.
UVM, Perl, Python, C
FY27 Intern - Edge AI and Display Hardware Architecture Development Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
Qualcomm Canada ULC needs candidates enrolled in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028 and graduating November 2028 or later. Strong analytical skills, programming in C/C++ or Python, and HW modeling and simulation experience are required.
Verilog, VHDL, C/C++, Python, HW simulation tools, HW CAD tools
SOC Design Engineer
Markham, ON +2Qualcomm Canada ULC
4+ YOECandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.
Spyglass, Design Compiler, Cadence LEC, Perl, TCL