ASIC/RTL Design Engineer 5 # 26-27793
Markham, ONContract
UT
US Tech Solutions
Candidates need strong ASIC synthesis and static timing analysis experience with EDA tools such as Design Compiler and PrimeTime. Experience with UPF/CPF, RTL coding in Verilog or SystemVerilog, and scripting in TCL, Perl, Python or Shell is expected.
Synopsys Design Compiler, PrimeTime, PrimePower, Power Artist
Verification Engineer 5 # 26-27787
Ottawa, ONContract
UT
US Tech Solutions
10+ YOECandidates need 10+ years of verification experience on large ASIC projects or hardware-related software work, strong C/C++ on Linux, and UVM and SystemVerilog skills. Debugging with Gdb and Valgrind, Perl and Makefiles, and strong communication are also required.
UVM, SystemVerilog, Verilog, SystemC, Gdb, Valgrind