“PCIe switch” jobs in Canada – Page 2

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• 1mo

  Technical Staff Engineer - Design

  Burnaby, BC

  $107k–$226k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  12+ YOECandidates need a B.S. in electrical engineering with 12+ years of related experience, hands-on pad ring and bump map work for advanced SoC designs, and knowledge of IO standards such as SerDes, DDR, PCIe and CXL. Scripting skills in Tcl or Python are required.

  Orbit IO, ISP, Tcl, Python, Verilog, SVN

  1mo

  Technical Staff Engineer–Applications

  Burnaby, BC

  $107k–$226k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  12+ YOECandidates need a bachelor's degree in electrical engineering, computer science or computer engineering and 12+ years of industry experience. Strong PCIe, C/C++ and firmware debugging skills and customer-facing technical support experience are required.

  Switchtec, WinDbg, JTAG, protocol analyzer, logic analyzer, oscilloscope

  1mo

  ASIC Development Engineer

  Burnaby, BC

  $76k–$114k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  2+ YOECandidates need a Bachelor's in Electrical or Computer Engineering and 2+ years of relevant industry experience, or a Master's in the same field. They need strong C++ or Python scripting, debugging and problem-solving skills, and clear written and verbal communication.

  Verilog, VHDL, C++, Python

  1mo

  Engineer II- Design

  Burnaby, BC

  $76k–$114k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  2+ YOECandidates need a bachelor's or master's degree in computer, electrical or a related engineering field and 2+ years of relevant experience, with new graduates considered. Strong programming in Python or C, IC and SoC validation, and lab equipment experience are needed.

  protocol analyzer, oscilloscope, logic analyzer, prototype ICs and boards

  1mo

  Technical Staff Engineer-Applications

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  8+ YOECandidates need a bachelor's degree in electrical engineering, computer science or computer engineering and 8+ years of industry experience. Required skills include PCIe, C/C++ firmware and driver development, embedded RTOS work, lab debugging and customer-facing technical support.

  Protocol analyzer, Logic analyzer, Oscilloscope, Multimeter, WinDbg, JTAG tools

• 1mo

  Senior FPGA Designer

  Montréal, QC

  HybridFull Time

  E

  Exegy

  5+ YOEDiplôme en génie électronique, électrique ou informatique; Cinq ans ou plus d'expérience en conception FPGA; Maîtrise avancée du VHDL et/ou du Verilog

  Vivado, Git, Jenkins, Python, Linux

• 1mo

  Platform Applications Engineer Intern (8-month Co-Op)

  Vancouver, BC

  

  Astera Labs Early Career: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  Candidates need to be pursuing a bachelor's degree or higher in electrical engineering, computer engineering or computer science. They need programming experience in C, C++, C# or Python, and hands-on experience building and troubleshooting computer systems.

  protocol analyzer, high-speed oscilloscope, BERT

• 1mo

  Sr. Principal Program Manager, ASIC Design

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  10+ YOEAstera Labs needs a candidate with 10+ years in ASIC or SoC development, including 3+ years in technical program management. Candidates need hands-on knowledge of the chip design flow, EDA and CAD tools, and pre-silicon validation.

  CAD infrastructure, Emulation platforms, FPGA prototyping platforms

  1mo

  Senior Digital Design Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.

  SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl

  1mo

  Principal FW/SW Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  8+ YOECandidates need a bachelor's degree in a technical field and 8 to 12 years of embedded firmware experience. They must know embedded C/C++, Ethernet or high-speed connectivity hardware, and analog or mixed-signal tuning. A master's degree and Python or lab-instrument experience are preferred.

  Oscilloscope, BERT, Logic analyzer, GDB, Git, Jenkins

• 1mo

  Développeur logiciel senior - Systèmes embarqués - Senior Software Developer - Embedded Systems （ Future Opportunities ）

  Montréal, QC

  On-site

  

  Syntronic

  10+ YOE10 ans d'expérience en conception et validation de logiciels embarqués; Baccalauréat en génie électrique, logiciel ou équivalent; Maîtrise de C, C++, Linux embarqué, GNU et Buildroot

  gcc, gdb, U-Boot, Buildroot, Linux

• 1mo

  Technical Lead Manager, Infrastructure Hardware (Server and Network Systems)

  Toronto, ON

  HybridFull Time

  

  Cerebras Systems

  8+ YOECandidates need a B.S. or M.S. in computer science or electrical/computer engineering, or equivalent experience, plus 8+ years of technical leadership on server, network or infrastructure platforms. Deep knowledge of server architecture and networking fundamentals, and experience running multi-vendor programs, are required.

  Linux, PCIe, optics

• 1mo

  Sr. Embedded Software/Firmware Engineer

  Toronto, ON

  $175k–$225k/yrRemote

  

  Ethernovia, Inc.

  6+ YOECandidates need a Bachelor's or Master's degree in computer science or a related field and 6+ years of experience. Strong C/C++ skills, device driver and operating system knowledge (Linux, QNX or RTOS), and hands-on hardware experience with communication devices are required.

  Git, Perforce, Yocto, uboot

  1mo

  Senior ASIC (Front End) Design Engineer

  Toronto, ON

  Hybrid

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.

  Verilog, Perl, TCL, C/C++, Make

  1mo

  Senior ASIC Design Verification Engineer

  Remote in Canada

  Remote

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field, and at least 10 years of ASIC verification experience. Required skills include SystemVerilog, UVM, Python, TCL and C/C++, plus strong debugging and communication abilities.

  Verilog, UVM, Python, TCL, C/C++, SystemC

7 companies