Senior Director, Technology
Ottawa, ONQualcomm Canada ULC
10+ YOECandidates need a bachelor's in electrical engineering with 10 years of ASIC or IP development experience, or a master's with 8 years. They also need hands-on knowledge of Ethernet, UALink and OTN, HDL languages, SystemVerilog UVM and verification methods.
SystemVerilog, Verilog, VHDL, UVM, Unix/Linux, SVN
DSP Application Engineer, Principal
Ottawa, ONQualcomm Canada ULC
12+ YOECandidates need an electrical engineering degree and years of hardware applications or semiconductor experience, with deep knowledge of PAM4 signaling, DSP equalization, SerDes, Ethernet and optical communications. Hands-on skill with oscilloscopes, BERTs and VNAs, plus Python or C automation, is required.
Oscilloscope, BERT, VNA, Python, C
Cross-Functional Engineer, Staff
Toronto, ON +1Qualcomm Canada ULC
4+ YOECandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ YOECandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
Application Engineer, Sr Staff
Toronto, ONQualcomm Canada ULC
6+ YOECandidates need a bachelor's degree in electrical or computer engineering plus 6 or more years of hardware experience, or an equivalent advanced degree with fewer years. They need strong debugging skills, C/C++ for embedded systems, and Python for test automation.
Oscilloscope, BERT, Protocol analyzer
DFT Engineer, Senior
Toronto, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in an engineering or computer science field with 2+ years of hardware engineering experience, or a master's with 1+ year. They need hands-on DFT, ATPG, and test-pattern experience plus scripting skills.
Python, Tcl, Perl
Staff Engineer, Physical Design/Implementation
Toronto, ONQualcomm Canada ULC
3+ YOECandidates need a Master's degree with 3+ years or a Bachelor's with 4+ years of ASIC physical design experience. They need hands-on skill with industry chip design tools and strong knowledge of timing, power and clocking.
Cadence Innovus, Synopsys ICC2
Physical Design Engineer, Staff
Toronto, ONQualcomm Canada ULC
7+ YOECandidates need 7+ years of physical design experience and a Bachelor's in Electrical or Computer Engineering or equivalent. Low-power, SoC and advanced technology node experience are desired, along with strong analytical, scripting and collaboration skills.
EDA tools
Engineer
Markham, ONQualcomm Canada ULC
1+ YOECandidates need a bachelor's degree in engineering or a related field, plus 6 months to 2 years of experience in chip design, VLSI or digital design, including internships. They should understand digital logic and timing, know basic physical design steps, and have scripting skills in Python, Tcl, Perl or Shell.
Verilog, SystemVerilog, EDA tools
Firmware Engineer, Edge AI Silicon Validation (Embedded C)
Markham, ONQualcomm Canada ULC
2+ YOECandidates need at least 2 years of embedded firmware or silicon validation experience in C, plus a bachelor's degree and 4 or more years of ASIC validation work (or a master's with 3 years, or a PhD with 2 years). Strong debugging, lab equipment and communication skills are needed.
Oscilloscope, Protocol analyzer, JTAG debugger, FPGA prototyping system, Perforce, Git
SOC Design Engineer
Markham, ON +2Qualcomm Canada ULC
4+ YOECandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.
Spyglass, Design Compiler, Cadence LEC, Perl, TCL
Camera Design Engineer
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python
ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python
ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python