Sr. Principal Program Manager, ASIC Design
Toronto, ONAstera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
10+ YOEAstera Labs needs a candidate with 10+ years in ASIC or SoC development, including 3+ years in technical program management. Candidates need hands-on knowledge of the chip design flow, EDA and CAD tools, and pre-silicon validation.
CAD infrastructure, Emulation platforms, FPGA prototyping platforms
Senior Digital Design Engineer
Toronto, ONAstera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
2+ YOECandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.
SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl
Senior Design Verification Engineer
Toronto, ONAstera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
2+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 2 to 5 years of verifying complex chips. Hands-on SystemVerilog, UVM and C/C++ experience, including C/C++ integration with SystemVerilog, is required, as is authorization to work in Canada.
SystemVerilog, UVM, C/C++, Python, Perl, FPGA emulation platform