“ASIC simulation tools” jobs in Canada – Page 5

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• 29d

  FPGA Designer

  Ottawa, ON

  Full Time

  LO

  Lumentum Ottawa ULC

  Candidates need experience designing ASIC or FPGA logic in Verilog or SystemVerilog, including synthesis, timing and clock domain crossing, plus AMD (Xilinx) or Altera tools. Strong debugging skills and clear communication are required.

  Xilinx, Altera, Verilog, SystemVerilog

• 29d

  Senior SoC Design Engineer

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.

  Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl

• 29d

  Senior Analog RF Design Engineer

  Ottawa, ON

  $117k–$187k/yrFull Time

  CC

  Ciena Canada ULC

  5+ YOECiena needs a Master's degree in electrical engineering or equivalent and 5 to 10 years of RF analog circuit design for telecom. Candidates need high-speed RF, op-amp and BiCMOS design experience, plus Cadence and mixed-signal simulation skills.

  Cadence Virtuoso, Cadence AMS, Calibre, HFSS, EMX, VNA

  29d

  ASIC Front End Implementation Engineer

  Ottawa, ON

  Full Time

  CC

  Ciena Canada ULC

  5+ YOECandidates need a B.Sc. in electrical or computer engineering and 5+ years of ASIC digital design and DFT experience. They must have hands-on DFT and synthesis tool skills and be able to work well in engineering teams.

  Synthesis tools, Static timing analysis tools, DFT tools, EDA tools

• 29d

  Field Application Engineer - AMD/Xilinx

  Pointe-Claire, QC

  Full Time

  AC

  Avnet Canada

  8+ YOECandidates need systems-level experience with FPGA and ASIC design tools, especially Vivado/Vitis, ISE or Quartus. They also need strong communication and problem-solving skills and typically 8+ years of experience with a bachelor's degree or equivalent.

  Vivado, Vitis, ISE, Quartus, ModelSim, IP Integrator

• 29d

  Staff Engineer, Diagnostic Development

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  5+ YOECandidates need a bachelor's or master's degree in computer engineering, computer science or a related field, plus 5+ years in semiconductor SoC/IP diagnostics, embedded systems or a similar area. Strong C/C++, Python and shell scripting skills and hardware/software debugging experience are required.

  JTAG, Python, C/C++, Shell scripts, Open-source debugging utilities

  29d

  Signal Integrity Engineer

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  5+ YOECandidates need a Bachelor's in electrical engineering or equivalent and 5+ years of high-speed PCB or package design at 10Gbps and above. They must know metrics like ICR, ERL, COM, NEXT and FEXT, be skilled in Cadence Allegro, and communicate clearly.

  Cadence Allegro

• 29d

  Hardware Intern - AI HW & SoC (Canada)

  Ottawa, ON +1

  

  Tenstorrent University Jobs: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need to be students in EE, ECE, CE or CS with coursework in digital design and computer architecture. They should know ASIC concepts such as RTL, verification, logic synthesis and timing analysis, and have scripting or programming skills.

  Python, C++, PERL, tcl, architectural simulator

• 29d

  Sr. Principal Program Manager, ASIC Design

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  10+ YOEAstera Labs needs a candidate with 10+ years in ASIC or SoC development, including 3+ years in technical program management. Candidates need hands-on knowledge of the chip design flow, EDA and CAD tools, and pre-silicon validation.

  CAD infrastructure, Emulation platforms, FPGA prototyping platforms

• 29d

  Senior ASIC (Front End) Design Engineer

  Toronto, ON

  Hybrid

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.

  Verilog, Perl, TCL, C/C++, Make

  29d

  Senior ASIC Design Verification Engineer

  Remote in Canada

  Remote

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field, and at least 10 years of ASIC verification experience. Required skills include SystemVerilog, UVM, Python, TCL and C/C++, plus strong debugging and communication abilities.

  Verilog, UVM, Python, TCL, C/C++, SystemC

8 companies