Senior ASIC (Front End) Design Engineer
Toronto, ONHybrid
Ethernovia, Inc.
10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.
Verilog, Perl, TCL, C/C++, Make