Static Timing Analysis (STA) Engineer
Toronto, ONFull Time
A
Altera
6+ YOECandidates need 6+ years of static timing analysis experience on ASIC or FPGA designs, plus a strong grasp of STA fundamentals and tools such as PrimeTime. A bachelor's or master's degree in electrical or computer engineering, with RTL design knowledge, is required.
PrimeTime, Verilog, SystemVerilog, Tcl, Python