Candidates need to be pursuing a Bachelor's degree in computer or electrical engineering, engineering science, computer science, mathematics or a similar field. They also need at least 3 months of experience or coursework in C/C++, Python, digital logic, FPGAs or Verilog.
Candidates need to be pursuing a bachelor's degree in computer science, electrical or computer engineering, or a related field. They need C/C++ experience and basic knowledge of digital logic and FPGA or ASIC concepts.
Candidates need to be currently pursuing a BS in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or a related field. They need at least 3 months of Verilog, SystemVerilog or VHDL design or verification experience and 3 months of Python, TCL, Perl, C or C++ experience.
8+ YOECandidates need a Bachelor's or Master's degree in an engineering or computer science field and 8+ years building compilers, LLVM/MLIR tools or EDA/FPGA software. They must know production C++, MLIR or LLVM, FPGA design and implementation flows, and be able to mentor engineers and work with customers.
3+ YOECandidates need a bachelor's degree in computer science or electrical or computer engineering, with 3+ years of experience. Required skills include C/C++, compiler concepts and digital logic and FPGA/ASIC hardware flows.
2+ YOECandidates need a bachelor's degree in an engineering or computer science field, 2+ years of digital hardware design or verification (SystemVerilog, Verilog or VHDL), and 2+ years of scripting or software programming (Python, TCL, Perl, C or C++).