3+ YOECandidates need a Bachelor's or Master's in computer science or electrical/computer engineering, plus 3+ years of verification experience. Required skills include Verilog, SystemVerilog UVM, cryptography, secure boot, AXI/AHB, and scripting in Python or Perl.
Candidates need experience in ASIC/SoC build or front-end CAD, strong Python and Tcl skills, and knowledge of RTL, Verilog/SystemVerilog and verification methods such as Lint, CDC and formal. They also need experience building production CAD flows, a degree in electrical or computer engineering or computer science (or equivalent experience), and an AI-first approach to automation.
7+ YOEArm needs candidates with a Bachelor's or Master's degree in computer science or electrical or computer engineering and 7+ years of PCIe or CXL verification experience. They must have strong Verilog and UVM skills, simulation and emulation experience, and knowledge of formal methods.
5+ YOEArm needs candidates with a Bachelor's or Master's degree in a related engineering or computer science field and 5+ years of SoC or compute subsystem design experience. Candidates need Verilog, PCIe, CXL or Ethernet integration experience and scripting skills in Perl or Python.
4+ YOECandidates need a Bachelor's or Master's degree in a related engineering or computer science field and 4+ years of PCIe or CXL verification experience. Strong skills in Verilog, UVM, debugging and simulation or emulation platforms are required.
10+ YOECandidates need a Bachelor's or Master's degree in computer science or electrical or computer engineering, 10+ years designing complex SoCs or compute subsystems, and strong Verilog and digital design skills. Experience with PCIe, CXL, UCIe or Ethernet subsystems and static design checks is required.
ARM needs a degree in computer science or electrical or computer engineering and a proven record of leading hardware design of compute, multimedia or security subsystems. Candidates need hands-on experience with Verilog RTL, cryptography, secure boot, SoC architecture and scripting.
5+ YOECandidates need a Bachelor's or Master's in computer science or electrical or computer engineering, plus 5+ years of design or verification experience. They must know security hardware verification, secure boot, key management and digital hardware design.
20+ YOECandidates need a bachelor's degree in science or engineering, with a master's preferred, and 20+ years in SoC architecture and hardware design. At least 5 years architecting clock, reset, power and thermal solutions and leading a mid-size global team are required.
Candidates need extensive security experience in applied cryptography, secure boot and key management, plus SoC security architecture on ARM or x86. They also need side-channel threat expertise, platform security knowledge and experience leading security teams.
Candidates need experienced SoC security architecture skills, including cryptographic design, firmware security and threat modelling. Familiarity with certifications such as PSA Certified, ISO/SAE 21434, FIPS 140-3 and Common Criteria is required.