Candidates need to be enrolled full-time in a BS in electrical or computer engineering, with coursework in digital circuits and computer architecture. Experience with Verilog or SystemVerilog and C, C++ or Python is needed, and prior hardware projects are an asset.
Candidates need an electrical engineering background (undergraduate or graduate), some coursework in analog design or layout, and experience with CAD tools for layout. Excellent English communication for presenting to global teams is required.
Candidates need to be full-time BS students in electrical engineering, computer engineering, or a related field. They need coursework in digital logic and computer architecture, plus experience with C, C++, Python, Verilog, or SystemVerilog.
6+ YOECandidates need 6+ years as a mixed-signal IP designer and, preferably, 6+ years as an engineering project manager in semiconductors. They also need knowledge of SoC/IC design flows, strong communication and leadership skills, and a broad background in ASIC or microelectronics development.
Program management, Interpersonal skills, Communication skills, Leadership, Risk management, Electrical engineering
Candidates need to be currently pursuing a BS in computer science, electrical engineering or a related field, with at least one year of related coursework. Strong C and Python programming, English communication and problem-solving skills are preferred.