Technology Lead-Memory Layout
CanadaInfosys
5+ YOECandidates need 5+ years of compiler or custom memory layout experience, including leafcell library design and FinFET layout at 5nm and 3nm. They must know physical verification (DRC, LVS, ERC) and use Cadence Virtuoso and Calibre, plus a bachelor's degree or equivalent experience.
Cadence Virtuoso, Calibre