Analog and RF Layout Engineer
Toronto, ONCapgemini
6+ YOECandidates need 6+ years of analog and RF IC layout experience for high-speed applications, including advanced FinFET nodes (7nm and below). Hands-on use of Cadence, Mentor and Synopsys EDA tools and knowledge of floorplanning, routing and electromigration are required.
Cadence, Mentor, Synopsys
Analog and RF Layout Engineer
Toronto, ONCapgemini
6+ YOECandidates need 6+ years of analog, RF or mixed-signal IC layout experience, including advanced FinFET nodes at 7nm and below. They need hands-on skill with Cadence, Synopsys or Siemens EDA tools and strong knowledge of DRC, LVS and reliability constraints.
Synopsys, Siemens EDA, Mentor Graphics