Principal Analog Mixed Signal Designer - 19497
Mississauga, ONSynopsys
5+ YOECandidates need a PhD with 5+ years or a Master's with 8+ years of hands-on analog IC design experience. Strong CMOS skills, detailed SerDes sub-circuit design experience and SPICE simulation expertise are required.
SPICE simulators, Verilog-A, schematic entry tools, physical layout tools, MATLAB, Python
IT Reliability, Site Associate
CanadaSynopsys
Candidates need a bachelor's degree in a related field, hands-on experience across Linux and Windows, and scripting ability in Bash, PowerShell or Python. Strong methodical troubleshooting and clear English communication are required.
Citrix, Linux, Windows, PowerShell, Bash, Python
Sr Manager or Principal Engineer for Firmware Development - 19315
Markham, ONSynopsys
10+ YOECandidates need a Bachelor's, Master's or PhD in computer or electrical engineering, or equivalent experience, with 10+ years in a related field. They need strong skills in digital logic and firmware development, proficiency in C, Verilog and SystemVerilog/UVM, and experience leading complex projects.
Verilog, UVM, C, Python, Perl, Bash
ASIC Digital Design, Sr Staff Engineer-19314
Markham, ONSynopsys
8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.
Verilog, SystemVerilog, UVM, VMM, Jira, Confluence
Hardware Engineering, Staff Engineer- 19028
Nepean, ONSynopsys
Candidates need proven experience with high-speed interface signaling, signal and power integrity analysis, and EDA tools such as HFSS, Ansys, HSPICE, Raptor and ADS. They also need strong communication skills and board-level and on-chip IO design knowledge.
HFSS, Ansys, HSPICE, Raptor, ADS
Principal Analog Design Engineer-19318
Markham, ONSynopsys
6+ YOECandidates need a PhD with 6+ years or a Master's with 8+ years of analog and mixed-signal IC design experience, including FinFET circuit design. Strong transistor-level CMOS and SPICE simulation skills are required.
Spectre, HSPICE, Verilog-A, schematic entry tools, Python, Perl
R&D Engineering, Staff Engineer
Ottawa, ONSynopsys
7+ YOECandidates need 7-8+ years of experience with a bachelor's degree, 5-6+ with a master's, or 3-4+ with a PhD, in an engineering or computer science field. They need strong skills in CAD or simulation infrastructure, scripting in Python, Tcl or Shell, and Linux environments.
Synopsys EDA design suite, Linux, Python, Tcl, Shell
Analog Design, Architect - 18618
Mississauga, ONSynopsys
10+ YOECandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.
SPICE, Verilog-A, TCL, Perl, C, Python
CAD Software Engineer, Principal-18736
Nepean, ONSynopsys
10+ YOESynopsys needs candidates with an MS or PhD in Computer Science or Electrical Engineering and at least 10 years of industry experience. They should be strong in Python, Perl, TCL, UNIX/Linux, Git, and Perforce, and have hands-on experience with Custom Compiler/Virtuoso.
Custom Compiler, Virtuoso, Git, Perforce, UNIX, Linux