IP Design PEY Intern
Toronto, ONFull Time
AS
Altera Semiconductor Technology Canada ULC
Candidates need to be currently pursuing a BS in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or a related field. They need at least 3 months of Verilog, SystemVerilog or VHDL design or verification experience and 3 months of Python, TCL, Perl, C or C++ experience.
Quartus Prime, Verilog, SystemVerilog, VHDL