Senior Mixed-Signal Designer - Acacia (Hybrid)
Kanata, ONCisco
5+ YOECandidates need a degree plus 5 to 12 years of related experience, depending on the degree level, and experience designing, simulating and measuring high-speed ICs across at least three of: SerDes, output drivers, PLLs, clock distribution, op-amps/PGAs or equalization. Experience with FinFET, layout and design tools is preferred.
Cadence Virtuoso, Spectre/APS/SpectreX, Calibre, EMX, Matlab
Principal Analog/mixed-signal IC Developer - Acacia (Hybrid)
Kanata, ONCisco
7+ YOECandidates need a Bachelor's with 15 years, a Master's with 10 years, or a PhD with 7 years of related experience. They must have high-speed IC design experience in at least three areas and have led a high-performance circuit team.
Cadence Virtuoso, Calibre, EMX, Matlab
Senior Analog/mixed-signal IC Designer - Acacia (Hybrid)
Kanata, ONCisco
12+ YOECisco candidates need 12+ years of experience with a BSEE, 8+ with an MS, or 5+ with a PhD. Experience in high-speed IC design in at least three areas such as SerDes, PLLs, output drivers, equalization and amplifiers is required.
Cadence Virtuoso, Spectre, Calibre, EMX, Matlab