Senior I/O Chiplet RTL Design Engineer
Ottawa, ONFull Time
BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.
10+ YOECandidates need 10+ years of hands-on ASIC RTL design with tape-out ownership, strong SystemVerilog and Verilog skills, and experience with high-speed interfaces such as PCIe, Ethernet or die-to-die links. They also need synthesis, timing constraint and CDC/RDC expertise, plus scripting in Python or Tcl.
SystemVerilog, Verilog, Python, Tcl