Staff/Sr. Staff Design Verification Engineer
Toronto, ONLightmatter
8+ YOECandidates need a bachelor's degree in an engineering field and at least 8 years of design verification and SystemVerilog experience. Python experience of 2 or more years, expertise with the UVM library and experience with Xcelium, ModelSim, Questa or VCS are also required.
Xcelium, ModelSim, Questa, VCS, UVM, SystemVerilog