“Cadence LEC” jobs in Canada

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• 10d

  SOC Design Engineer

  Markham, ON +2

  On-site

  

  Qualcomm Canada ULC

  4+ YOECandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.

  Spyglass, Design Compiler, Cadence LEC, Perl, TCL

  1mo

  Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.

  SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools

• 27d

  Physical Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's degree in an electrical, electronics or computer engineering discipline and deep experience in ASIC physical design implementation and signoff. They also need hands-on skill with industry EDA tools and power, performance and area optimization.

  Synopsys ICC2, Cadence Innovus, PrimeTime, Spyglass, RedHawk, Calibre

  27d

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  27d

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

• 1mo

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1mo

  Physical Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  8+ YOECandidates need a bachelor's, master's or PhD in electrical, electronics or computer engineering, with 8, 4 or 2 years of physical design experience respectively. They need expertise in block-level place and route, timing closure, physical verification and power, performance and area optimization, plus hands-on debugging of EDA tools from Synopsys, Cadence and Siemens.

  Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, Spyglass, RedHawk, Calibre

  1mo

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

• 1mo

  Senior Physical Design Engineer - P&R

  Ottawa, ON

  RemoteFull Time

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  8+ YOECandidates need 8 or more years of ASIC digital place-and-route experience, recent hands-on work with Synopsys and Cadence tools, and knowledge of advanced FinFET nodes. Scripting skills and strong written communication for remote teamwork are also required.

  Synopsys, Cadence, PrimeTime, StarRC, RedHawk, Calibre

• 1mo

  Principal Engineer -Design

  Saskatoon, SK

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  10+ YOECandidates need 10 years of experience in synthesis, static timing analysis and formal verification, plus tapeout experience on 16nm or smaller processes. Strong scripting skills and a degree in computer science or electrical/VLSI engineering are required.

  Cadence Genus, TCL, Perl, Python, UPF, CPF

5 companies