RTL Engineer
Burnaby, BC$106k–$158k/yrFull Time
SS
SEL Schweitzer Laboratories, Inc.
5+ YOECandidates need a B.S. in Electrical Engineering or equivalent, plus 5+ years of combined FPGA RTL design in VHDL or Verilog, firmware in C/C++, and functional verification experience. Strong technical writing, teamwork and mentoring skills are required.
VHDL, Verilog, Xilinx tools, Intel FPGA (Altera) tools, Microchip (Microsemi/Actel) tools, Lattice Semiconductor tools